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SONY
CXD1160AP/AQ
Outline
of Serial I/O
timing
SI
SO
LRCK
\
ch
1
data
'fori 2 data
fi
1
1
1
1
/
""Calculating operations"-
^
'jX* ch
1
input register
)
\
\
*(•
ch 2
input register
(
ch
1
output
register
-t"
H
ch
1
data-jfch 2
data
T
<
ch 2
output
register
.)-'
Firsl,
during
1LRCK
period,
ch1/eh2
serial
data
that
is
input
from
SI
is
latched
at
ch1/ch2
input register with
the
rising
edge
of
the
following
LRCK.
Also,during
1
LRCK,
if
the
results
of
the calculating
operations are
enclosed
into
chl/ch2
output
registers,
those
are latched
by
the
Shift
register
at
the following
rising
edge
of
LRCK
to
be
respectively output
as
serial
data from
SO.
Detailed timing
between
Serial
I/O
and
I/O register
is
as
follows.
r
LRCK
bck
n
r
SI/SO ~~
K
2SB
It
LSB
f
_T
Period during
which
gate
latch
is
applied
to
chl/ch2
input registers.
T
ch1/ch2
output
registers
value
latched
at
shift
register.
Serial I/O
and
I/O register
are
dependent on
the timing with
LRCK
and
BCK
from
the
exterior.
Also
the only
interrupt
is
executed
between
this
LRCK
and
BCK
on
the
Instructions.
The
IC
operates on
the
master
clock.
Now,
should the
operation
be
going
on
in
1LRCK
period
at
cycle
to
cycle L (L+1
cycle),
the following
restrictions
would
apply
to
the
I/O
register
handling.
<lnput
register
read
command>
Cycle
(L-3),
(L-2),
(L-1),
L
cannot
read.
Cycle
to
cycle
(L-4)
can
read.
<Output
register write
command>
The
following are
standards
of
cycles
where
write
cannot be executed
in
the output
register.
This
is
because
of
the
frequency
relationship
between
bit
clock
BCK
and
cycle clock
KCK
(ICK).
Order
of
cycle
24
clock
mode
32
clock
mode
L-3
I2KCK
2
LRCK
2
16KCK
SsLRCKa
L-2
60KCK
"
8QKCK
"
L-1
108KCK
"
H4KCK
"
L
all
all
LRCK
£
IS2KCI
LRCKS176KCK
1
LRCK
2
ISO
LRCK
S
240
2
LRCK
£
228
LRCK
fi
304
ii
LRCK
£
132+48n
LRCK
£
176+64
n
-
124-
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