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SONY
(5)
Zero
detect function
Q)
Operation
The
input
data
controls the operation
of
zero
detection
and
when
continuing
for
zero data
detect time •
,
zero
mute
flag
(FLGL,
FLGR)
**
is
active.
*
Note
1
:
See
section
on System
mode
(6)
zero data
detect period.
** Note
2:
See
section
on
(6)
Mute
circuit
control.
©
Zero
detect
method
The
zero data detect
section consists
of
a low-level detect
and a
DC
detect section.
When
both Low-level
and
DC
conditions are present,
zero
detect occurs.
MSB
_SQ
Input data
CIS-bit
example)
1
2|3|4
e
8
,'
-.
10
1
i?
3
14|15 16
|l7|l8|
DC
detect
Low-level delect section
section
j
Zero
data detect section structure
The
low-level
detect section
senses whether
the input data's
first
14-bit
are
ALLO
or
ALL1.
The
DC
detect section
senses
the
input
data doesn't
change.
When
16-bit
data
is
input.
DC
detection section consists
of
bit-
15
and
bit-16.
When
18-bit
data
is
input,
DC
detection section consists
of
bit-1
5 through
bit-18.
(6)
Mute
circuit
operation
(D Zero mute
flag
(FLGL,
FLGR)
operation
The
zero
mute
flag
operations according
to
the block
diagram
below.
The
mute
circuit
controls
this
operation.
F
"v
DAC
~-
Mute
CTCuit
(CXD2560VI)
1
1
FLGL,
FLGR
Mute
flag
block
i
Jiagram
on
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