Sony CXD2701Q Data Book page 66

SONY
CX32860M
(7)
I/O synchronization
circuit
(D Theory
of
operation
The
synchronizing
circuit
opens
a
window
for
eight
internal
system
clocks
(one clock=256Fs)
to
monitor
whether
the
differentiated signal of
the
rise of
LRCKI (LRCKI J")
that
may
be
input
is
present.
If
the
LRCKI
_f is
out of the
window when
the power
supply
is
turned on, the synchronizing
circuit
holds
it
at
the time
it
is
in
the center
of
the window, and
lets
it
start
as soon
as the next
LRCKI
_f arrives.
This process
synchronizes
both
an
external system and
this
LSI
itself.
®
IN IT
re-synchronization cycle
If
the
LRCKI
_f
is in
the
window when
the
power
supply
is
turned
on.
a
fluctuation of
LRCKI
could
cause
re-synchronization during operation
of
the
IC. particularly
when
it
is
at either
end
of
the window. Thus
it
is
important
to
re-initialize
the
system
after turning the
power
on.
Re-
synchronization
is
performed
at
the time
that
INtT
goes
high (J~),
initialize
synchronization
circuit
and
then
positions
LRCKI
J"
in
the center
of
the
window.
©
Operation
when
I
NIT
is
pulled
"L".
Set
input
data
to
zero
data.
Set output data
to zero
data.
Output
clocks
(LRCKO, BCKO.
128Fs)
are continuously
output.
Noise shaper
register
is
cleared.
IIR register
is
cleared.
zero
mute
flag
(FLGL,
FLGR) becomes
active.
©
Initialization
process
after
power ON.
After
Vdd
reaches over 4.75V
and
the
MCLK
stabilizes, input 8
CK
or
more.
Then
bring INIT "H"
to
complete
the
initialization.
(8)
I/O
signal latch timing
©
Input
ATT, SHIFT,
LATCH: when
INIT and
CTL
are
pulied
"H",
These
input signals are latched
to
LRCKI
by
the appropriate
internal
clock
.
@
Output
LRCKO,
DL,
DR:
These
output signals are latched
to
BCKO
by
the appropriate
internal clock.
(9)
384Fs
oscillation
synchronized by
128Fs
In
CD
applications
utilizing
DSP,
it
is
possible
to
supply
the
master
CK
(384Fs).
62