Sony CXD2701Q Data Book page 117

o|-V|^.-y CXD1160APJAQ
Operation
Block
Diagram Description
(1JI-RAM
l-RAM
Instruction
RAM
with
command
word
length of
24bit x
64
word.
Write
in
from the
exterior
possible
through
microcomputer
interface,
Commands
are divided into 1/2/3/
cycle
commands
according
to type.
Jumps
to
No.
every sampling
cycle.
1
-address stack
6bit
address 2-stage stack
Combination
with
double sub routine or
loop
jump
is
possible,
Loop
Counter
4bt loop counter.
Loop jump
possible
from
to
15
times.
(2)
K-RAM
K-RAM
I6blt
x 64 word
coefficient
RAM.
Write
in
from the exterior
can be performed
through
the
microcomputer
interface
as well
as
write
through execution
command
coefficient
is
in
the
format of
complement on two while
single precision (16b)
and double
precision (32b) are
handled
concurrently.
(3)
D-RAM
p.RAlvi I6bit
x 64 word
data.
Address space
is
ring
shaped while the
method
adopted
is
tor
users to
make
access without
knowledge
of
the physical address.
Data
is
in
the format
of
complement on two with single (16b)
and double
precision (32b) are
handled concurrently.
D-address Counter
6bit
long
address
counter
counted up
every sampling cycle.
Users are
aware
of
the
address relative to that of
the
address counter value.
The counter
indicates the actual physical
address
and can be handled as a
delay tap
fixed
address.
(4)
Data
Register
(all in
complement on
two
format)
511
Register
This register
(32b) stores
CH1
data input
from
serial I/O
used
for
read only.
Upper
16bit
(11
H)
and
lower 16bit
(ML)
can be handled
independently.
512 Register
This
register
(32b) stores
CH2
data
input
from
serial I/O
used
for
read only,
Upper
16bit (I2H)
and lower
I6bit (I2L)
can be handled
independently.
501
Register
This register
(32b) stores
CH1
data output
from
serial I/O.
Beside
read/write,
can
also
be handled as
a temporary
register,
upper
16bit
(01H),
and lower
16bit
(01
L)
can be
handled independently.
502
Register
This
register
(32b) stores
CH2
data output
from
serial I/O.
Beside read/write,
can
also
be
handled as a temporary
register.
Upper
1
Bbit
(02H) and
lower I6bit
(02L)
can be
handled
independently.
Dl
Register
This register
(32b) stores
CH1
or
CH2
data input
from delay
I/O.
Used
for
read
only.
Upper
16bit
(DIH)
and
lower
16bit (DIL)
can be handled independently.
DO
Register
This
register
(32b) stores
CH1
or
CH2
data
output from delay
I/O,
Used
for write
only.
Upper
I6bit
(DOH) and lower
16bit
(DOL) can be
handled separately.
P
Register
This
register 33bit
in
length,
stores the
multiplied results of
various
bit
lengths.
R
Register
Data
set in
this
register
(32b)
through the transfer
command
can be
utilized
as
one sided
input to
AV. Upper
16bit
(RH)
and lower
16t.it
(RL)
can be
set
independently.
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