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SONY
CXD27Q1Q
DSP
Block Diagram Explanation
FIR
i
1
1th-order
FIR
(liter,
using
1/2fs
down
-samp
ling.
FIR o
1
Uh-order FIR
filter,
with
DSP
signal
processing
by
1/2fs signals,
the
original fs
is
done
by
up-sampling.
A/D
L-ch Register
Register
for storing
L-channel data
1
6-bit
Input
from FIR1
,
(ADL)
A/D
R-ch
Register
Register
for storing
R-channel data
16-bit
input
from FIR1.
(ADR)
D/A
L-ch Register
Register
for
storing
L-channel data
1
6-bit
output from FIR2.
It
can
also
be used
as
the
Ist-degree
addition
register.
(DAL)
D/A R-ch
Register
Register
for
storing
R-channel data
1
6-bit
output
from
FIR2.
It
can
also
be used as
the
1
st-degree
I/O instruction
data output
register.
(DAR)
R1
Register
R2
Register
K-RAM
MOP
Register
MPY
P
Register
AOP
Selector
ADDER
Ace
Register
Clipper
Register
for
storing
accepted data
1
6-bit
during the
I/O
process. (R1
)
Register
for
storing
R1
register
data
16-bit
by
transfer
instructions.
(R2)
RAM
for
storing
two's
complement
format
multiplication coefficient 8-
bit.
(K)
Register
for
storing
the
multiplication
data
16-bit
selected
from
the various
multiplication
instructions.
ADL,
ADR.
R1
,
Ace
(16).
(MOP)
Executes each
operation
in
sequence:
MOP
(1
6)
xK
(8)
-•
P
(20).
Register
for
storing result
of
multiplication 20-bit of
a
16-bit multiplied
by
an
8-bit.
(P)
Selector
for
selecting
from
DAL,
R2, Ace, or
Null,
and
converting
to
22-bit
format according
to
the
addition
instruction of
each
step.
Executes each
operation
in
sequence:
AOP
(22)+P
(20)
-*
Ace
(22).
Register
for
storing result
of
addition
22-
bit
of
a
22-bit multiplied
by a
20-bit,
(Ace
(22),
Ace
(16))
The
result of
addition 22-bit
Ace
(22)
is
used
unchanged
by
the
following 22-bit addition
instruction.
In
other
instructions,
that
is
16-bit.
When
an
overflow occurs, the
clipper
processing outputs
16-bit
Ace
(16).
-
194-
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