Sony CXD2701Q Data Book page 54

SONY
Pin
Configuration
(Mini-fiat
package)
Pin Description
Vss
i^
©FLGR
SYSM '2)
©FLGL
ATT
^3
)
©LRCKO
SHIFT
aj
@DR
LATCH
5
)
@DL
CTL{
e)
Top
©BCKO
INIT r\
View
@VDO
BCKI
y
©MCLK
DATA!
S
©INV02
LRCKK
icj
©INVO
TEST(
1
}
©INVI
Vss
J?)
@«28Fs
Pin No. Symbol
I/O Description
1
Vss Power
supply
(0V)
2
SYSM
1
System mute
input.
"H":
FLGL
and
FLGR
outputs
active.
3
ATT
1
When CTL
"L":
ATT
data input
CTL
"H":
EMP
input.
4
SHIFT
1
When CTL
"L": shift
clock
input.
CTL
"H":
FS32
input.
5
LATCH When CTL
"L":
latch
clock
input.
CTL
"H":
FS48
input.
6
CTL
Fixed
internally at "L" level. "H": direct input
mode.
"L":
serial
transfer
mode.
7
INtT
Re-synchronized by
rising
edge
of this signal
8 BCKI
BCK
input
9
DATAI
Data
input
10
LRCKI
1
LRCK
input
11
TEST
1
Test
pin.
Fixed
at "L" level
in
normal
operation
mode.
12
Vss
Power
supply
(OV)
13
128 Fs
1
28 Fs
clock output
14
INVI
1
Inverter input
15
INVO
Inverter output
(INVi)
16
INV02
Inverter output
(IFJVS)
17
MCLK
1
Master
clock input
(f=51
2Fs)
18
Voo
—
Power
supply (+5V)
19
BCKO
BCK
output
20
DL
L-
channel data output
21
DR
R-channel
data output
22
LRCKO
'
LRCK
output
23
FLGL
L-channel zero muting
(lag
output
2.4
FLGR
R-channel zero muting
flag
output
-50-