Sony CXD2701Q Data Book page 155

SONY,
CXD1160AP/AQ
Serial
10
and Register
(1)
Serial I/O input register
The
conditions
for
transfers with serial
I/O input register
as source
of for
cycle
n
without
MPY
are:
1
3
N-4
—
<n <
N-2—
*M
4
4
SIN
delay from
M
- BCK
falling
edge
As
M=2—
CKCK]
4
fKCK
fS
for
whole number
iK-4
£n KH-D
=
ISi-4*b SN,-1)
Cycle
to
cycie (Nt-5)
Serial input
data transferred to
the previous
sampling space
is in
this
space
register
and can
be handled
freely.
Cycle
(N,-4) to cycle (Ni-1)
In
this
space usage
of serial
I/O input register
is
prohibited.
*
In
certain
cases cycle (Ni-2)
can be
used.
Check when
necessary.
fKCK
fS
for
whole
number
n=
iN-4
Srt
SN-1
I
(Ni-4Sn 5N,I
Cycle
to
cycle (Ni-5) Serial input
data
transferred
to
the previous
sampling
space
is
in this
space
register
and can be
handled
freely.
Cycle
(Ni-4)
to
cycle Ni
In this
space usage
of serial
I/O input register
is
prohibited.
(2)
Serial I/O
output register
Cycle n conditions
for
transfers that
can
not
be
executed with
serial
I/O
output register
as
destination
I
1
fKPK
T TKCK
N-4—
t
-^
-H<n
< K-2--
I
-^
fB
...
bit
clock
frequency
4
fB 4 fB
M
is
a
delay
margin
to
be
ignored here
l
fKCK
\-o—
-
'
re
fB
24
bit
clock
system
1 1
fKCK
3
1
fKCK
32
bit
clock
system
1 1
fKCK
N-4—
+
i
84
fS
3
1
fKCK
<n <
N-2
—
4
—
tt"
4
64
fS
As no
margin
is
taken
for
the
left
side,
in
certain
cases
prohibited cycles are
not included.
Check
when
necessary.
-151-