Xilinx DPU IP Product Manual page 15

Register
Reg_dpu0_base_addr0_l
Reg_dpu0_base_addr0_h
Reg_dpu0_base_addr1_l
Reg_dpu0_base_addr1_h
Reg_dpu0_base_addr2_l
Reg_dpu0_base_addr2_h
Reg_dpu0_base_addr3_l
Reg_dpu0_base_addr3_h
Reg_dpu0_base_addr4_l
Reg_dpu0_base_addr4_h
Reg_dpu0_base_addr5_l
Reg_dpu0_base_addr5_h
Reg_dpu0_base_addr6_l
Reg_dpu0_base_addr6_h
Reg_dpu0_base_addr7_l
Reg_dpu0_base_addr7_h
Reg_dpu1_base_addr0_l
Reg_dpu1_base_addr0_h
Reg_dpu1_base_addr1_l
Reg_dpu1_base_addr1_h
Reg_dpu1_base_addr2_l
Reg_dpu1_base_addr2_h
Reg_dpu1_base_addr3_l
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Table 6: Reg_dpu_base_addr
Address Width Type Description
Offset
0x224 32 R/W
0x228 32 R/W
0x22C 32 R/W
0x230 32 R/W
0x234 32 R/W
0x238 32 R/W
0x23C 32 R/W
0x240 32 R/W
0x244 32 R/W
0x248 32 R/W
0x24C 32 R/W
0x250 32 R/W
0x254 32 R/W
0x258 32 R/W
0x25C 32 R/W
0x260 32 R/W
0x324 32 R/W
0x328 32 R/W
0x32C 32 R/W
0x330 32 R/W
0x334 32 R/W
0x338 32 R/W
0x33C 32 R/W
Chapter 2: Product Specification
The lower 32 bits of the base address0 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address0 of DPU core0.
The lower 32 bits of the base address1 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address1 of DPU core0.
The lower 32 bits of the base address2 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address2 of DPU core0.
The lower 32 bits of the base address3 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address3 of DPU core0.
The lower 32 bits of the base address4 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address4 of DPU core0.
The lower 32 bits of the base address5 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address5 of DPU core0.
The lower 32 bits of the base address6 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address6 of DPU core0.
The lower 32 bits of the base address7 of DPU core0.
The lower 8 bits in the register represent the upper 8
bits of the base address7 of DPU core0.
The lower 32 bits of the base address0 of DPU core1.
The lower 8 bits in the register represent the upper 8
bits of the base address0 of DPU core1.
The lower 32 bits of the base address1 of DPU core1.
The lower 8 bits in the register represent the upper 8
bits of the base address1 of DPU core1.
The lower 32 bits of the base address2 of DPU core1.
The lower 8 bits in the register represent the upper 8
bits of the base address2 of DPU core1.
The lower 32 bits of the base address3 of DPU core1.
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