Xilinx DPU IP Product Manual page 12

The DPU I/O signals are listed and described in Table 1.
Signal Name
S_AXI
s_axi_aclk
s_axi_aresetn
dpu_2x_clk
dpu_2x_resetn
m_axi_dpu_aclk
m_axi_dpu_aresetn
DPUx_M_AXI_INSTR
DPUx_M_AXI_DATA0
DPUx_M_AXI_DATA1
dpu_interrupt
Notes:
1. If only input ports are needed, you can edit the ports in the block diagram and declare at the port
interface level.
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Table 1: DPU Signal Description
Interface Type Width
Memory mapped 32
AXI slave interface
Clock 1
Reset 1
Clock 1
Reset 1
Clock 1
Reset 1
Memory mapped 32
AXI master interface
Memory mapped 128
AXI master interface
Memory mapped 128
AXI master interface
Interrupt 1~3
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Chapter 2: Product Specification
I/O Description
I/O 32-bit Memory mapped AXI interface
for registers.
I AXI clock input for S_AXI
I Active-Low reset for S_AXI
I Input clock used for DSP unit in DPU.
The frequency is two times of
m_axi_dpu_aclk.
I Active-Low reset for DSP unit
I Input clock used for DPU general logic.
I Active-Low reset for DPU general logic
I/O 32-bit Memory mapped AXI interface
for instruction of DPU.
I/O 128-bit Memory mapped AXI interface
for DPU data fetch.
I/O 128-bit Memory mapped AXI interface
for DPU data fetch.
O Active-High interrupt output from DPU.
The data width is decided by the DPU
number.
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