Xilinx DPU IP Product Manual page 21

DSP Usage
You can select whether DSP48E slices are used for the accumulation in the DPU convolution module.
If the low DSP usage is selected, the DPU IP will use DSP slices for multiplication only in the
convolution. In the high DSP usage mode, the DSP slice will be used for both multiplication and
accumulation. As a result, the high DSP usage consumes more DSP slices and less LUT. The difference
of logic utilization between high and low DSP usage is shown in Table 9. The data is tested on the
Xilinx ZCU102 platform without Depthwise Conv, Average Pooling, Relu6, and Leaky Relu features.
High DSP Usage
Arch LUT
B512 20177
B800 20617
B1024 27377
B1152 28698
B1600 30877
B2304 34379
B3136 38555
B4096 40865
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Table 9: Resources of Different DSP Usage
Register BRAM DSP
31782 69.5 98
35065 87 142
46241 101.5 194
46906 117.5 194
56267 123 282
67481 161.5 386
79867 203.5 506
92630 249.5 642
Chapter 3: DPU Configuration
Low DSP Usage
Arch LUT
B512 20759
B800 21050
B1024 29155
B1152 30043
B1600 33130
B2304 37055
B3136 41714
B4096 44583
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Register BRAM DSP
33572 69.5 66
33752 87 102
49823 101.5 130
49588 117.5 146
60739 123 202
72850 161.5 290
86132 203.5 394
99791 249.5 514
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