Dsp With Enhanced Utilization (Dpu_Eu) - Xilinx DPU IP Product Manual

DSP with Enhanced Utilization (DPU_EU)

In the previous DPU version, the general logic and DSP slices work in the same clock domain, though
technically the latter can run at a higher frequency. To enhance the utilization of DSP slices in DPU, the
advanced DPU_EU version was designed.
The EU in "DPU_EU" means enhanced utilization of DSP slices. DSP Double Data Rate (DDR) technique is
used to improve the performance achieved with the device. Therefore, two input clocks for DPU is
needed, one for general logic, and the other for DSP slices. The difference between DPU and DPU_EU is
shown in Figure 7.
All DPU mentioned in this document refer to DPU_EU, unless otherwise specified.
clk1x
IMG
A
ram
A+D
+
D
IMG
ram
×
WGT B
B
ram
DSP48 Slice
Port Descriptions
The DPU top-level interfaces are shown in the following figure.
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
M RES
Figure 7: Difference between DPU and DPU_EU
Figure 8: DPU_EU IP Port
Chapter 2: Product Specification
clk1x
IMG
A A A
ram Async DLY
+
IMG D D D
Async DLY
ram
WGT B0 B B
Async SEL
ram
DSP48 Slice
WGT
B1
ram Async
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clk2x
PCOUT
RES
A+D 0
M
×
P
PCOUT
+
B
PCIN
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clk1x
RES
OUT
0
0
DLY
RES OUT
1
1
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