Xilinx DPU IP Product Manual page 29

Dpu for convolutional neural network v1.2
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Chapter 5: Development Flow
Figure 18: DPU IP in Repository
Add DPU IP into Block Design
Search DPU IP in the block design interface and add DPU IP into the block design. The procedure is
shown in Figure 19 and Figure 20.
Figure 19: Search DPU IP
Figure 20: Add DPU IP into Block Design
DPU IP Product Guide
www.xilinx.com
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PG338 (v1.2) March 26, 2019

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