Register Space - Xilinx DPU IP Product Manual

Register Space

The DPU IP implements registers in the programmable logic. Table 2 shows the DPU IP registers. These
registers are accessible from the host CPU through the S_AXI interface.
Reg_dpu_reset
The reg_dpu_reset register controls the resets of all DPU cores integrated in the DPU IP. The lower three
bits of this register control the reset of up to three DPU cores respectively. All the reset signals are
active-High. The details of reg_dpu_reset is shown in Table 2.
Register
Reg_dpu_reset
Reg_dpu_isr
The reg_dpu_isr register represents the interrupt status of all DPU cores integrated in the DPU IP. The
lower three bits of this register shows the interrupt status of up to three DPU cores respectively. The
details of reg_dpu_irq is shown in Table 3.
Register
Reg_dpu_isr
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Table 2: Reg_dpu_reset
Address Width Type
Offset
0x004 32 R/W
Table 3: Reg_dpu_isr
Address Width Type
Offset
0x608 32 R
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Chapter 2: Product Specification
Description
[0] – reset of DPU core 0
[1] – reset of DPU core 1
[2] – reset of DPU core 2
Description
[0] – interrupt status of DPU core 0
[1] – interrupt status of DPU core 1
[2] – interrupt status of DPU core 2
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