Xilinx DPU IP Product Manual page 14

Reg_dpu_start
The reg_dpu_start register is the start signal for DPU core. There is one start register for each DPU core.
The details of reg_dpu_start is shown in Table 4.
Register
Reg_dpu0_start
Reg_dpu1_start
Reg_dpu2_start
BReg_dpu_instr_addr
The reg_dpu_instr_addr register is used to indicate the instruction address of DPU core. There are three
registers which are reg_dpu0_instr_addr, reg_dpu1_instr_addr, and reg_dpu2_instr_addr. The details of
reg_dpu_instr_addr are shown in Table 5.
Register
Reg_dpu0_instr_addr
Reg_dpu1_instr_addr
Reg_dpu2_instr_addr
Reg_dpu_base_addr
The reg_dpu_base_addr register is used to indicate the address of input image and parameters for DPU
calculation in the external memory. The width of dpu_base_addr is 40 bits so it can support an address
space up to 1 TB. All registers are 32 bits wide, so two registers are required to represent a 40-bit wide
dpu_base_addr. The reg_dpu0_base_addr0_l represents the lower 32 bits of the base address0 in DPU
core0, and the reg_dpu0_base_addr0_h represents the upper eight bits of the base address0 in DPU
core0.
There are eight groups of DPU base address for each DPU core and in total 24 groups of DPU base
address for up to three DPU cores. The details of reg_dpu_base_addr are shown in Table 6.
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Table 4: Reg_dpu_start
Address Width Type
Offset
0x220 32 R/W
0x320 32 R/W
0x420 32 R/W
Table 5: Reg_dpu_instr_addr
Address Width Type
Offset
0x20c 32 R/W
0x30c 32 R/W
0x40c 32 R/W
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Chapter 2: Product Specification
Description
Control the start-up of DPU core0.
Control the start-up of DPU core1.
Control the start-up of DPU core2.
Description
[0] –The instruction start address in
external memory for DPU core0.
[0] –The instruction start address in
external memory for DPU core1.
[0] –The instruction start address in
external memory for DPU core2.
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