Configuration Options - Xilinx DPU IP Product Manual

Element Wise
Concat
Reorg
FC
Notes:
1. The parameter channel_parallel is determined by the DPU configuration. For example, the
channel_parallel of DPU-B1152 is 12, the channel_parallel of DPU-B4096 is 16.

Configuration Options

You can configure the DPU with some predefined options which includes DPU core number, DPU
convolution architecture, DSP cascade, DSP usage, and UltraRAM usage. These options enable the DPU
IP configurable in terms of DSP slice, LUT, block RAM, and UltraRAM utilization. Figure 10 shows the DPU
configuration.
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Input channel
Input size
Output channel
Strides
Input_channel
Output_channel
Figure 10: DPU Configuration
www.xilinx.com
Chapter 3: DPU Configuration
1 – 256*channel_parallel
arbitrary
1 – 256*channel_parallel
stride * stride * input_channel <= 256 *
channel_parallel
Input_channel <= 2048*channel_parallel
Arbitrary
19
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