Xilinx DPU IP Product Manual page 4

Dpu for convolutional neural network v1.2
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Introduction .............................................................................................................................................................................. 33
Hardware Design Flow .......................................................................................................................................................... 36
Software Design Flow ............................................................................................................................................................ 39
Appendix A: Legal Notices ....................................................................................................................................................... 43
References ................................................................................................................................................................................. 43
Please Read: Important Legal Notices ............................................................................................................................ 43
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
www.xilinx.com
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