Chapter 3: Dpu Configuration; Introduction - Xilinx DPU IP Product Manual

Introduction

The DPU IP provides some user-configurable parameters to optimize the resources or the support of
different features. You can select different configurations to use on the preferred DSP slices, LUT, block
RAM, and UltraRAM utilization based on the programmable logic resources that are allowed. There is
also an option to determine the number of DPU cores that will be used.
The deep neural network features and the associated parameters supported by DPU is shown in the
following table.
Table 7: Deep Neural Network Features and Parameters Supported by DPU
Features
Convolution
Deconvolution
Max Pooling
DPU IP Product Guide
PG338 (v1.2) March 26, 2019
Description
Kernel Sizes
Strides
Padding_w
Padding_h
Input Size
Input Channel
Output Channel
Activation
Dilation
Kernel Sizes
Stride_w
Stride_h
Padding_w
Padding_h
Input Size
Input Channel
Output Channel
Activation
Kernel Sizes
Strides
Padding
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Chapter 3: DPU Configuration

W: 1-16 H: 1-16
W: 1-4 H:1-4
1: kernel_w-1
1: kernel_h-1
Arbitrary
1 – 256*channel_parallel
1 – 256*channel_parallel
ReLU & LeakyReLU
dilation * input_channel <= 256 * channel_parallel
&& stride_w == 1 && stride_h == 1
W: 1-16 H: 1-16
stride_w * output_channel <= 256 *
channel_parallel
Arbitrary
1: kernel_w-1
1: kernel_h-1
Arbitrary
1 – 256 * channel_parallel
1 – 256 * channel_parallel
ReLU & LeakyReLU
W: 1-16 H: 1-16
W: 1-4 H:1-4
W: 1-4 H: 1-4
18
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