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Table 7. PHY Address Configuration Settings (Jumpers JP66 - JP70)
Jumper / Label
JP66 / ADD_0
Address <4:0> - Sets base address. Each port adds its port number (starting with 0) to this
address to determine its PHY address.
JP67 / ADD_1
Jumper "open" sets address bit to 0.
JP68 / ADD_2
Jumper "Installed" sets address bit to 10.
Note: Do not select a base address higher than 24 to make all ports accessible within the 0 - 31
JP69 / ADD_3
PHY address range.
Port 0 = Base + 0
Port 1 = Base + 1
Port 2 = Base + 2
Port 3 = Base + 3
JP70 / ADD_4
Port 4 = Base + 4
Port 5 = Base + 5
Port 6 = Base + 6
Port 7 = Base + 7
4.4
Alternate MDIO Routing Configuration
The MDIO and MDC signals may be routed either through the 40-pin connector for MII Port 0 (the
standard configuration) or through a pair of RJ-11 connectors (J1 and J2), as shown in
either configuration the MII registers can be accessed for each port by setting the correct PHY
address. Refer to the LXT9781 Data Sheet for specific register definitions and functions. The
standard configuration is to route MDIO through the Port 0 MII connector to the SmartBits Test
Box by setting JP2 and JP3 to 2 - 3.
.
Table 8. MDIO Routing
MDIO
Port 0
Jumper
Comm
Port
JP3
2 - 3
1 - 2
JP2
2 - 3
1 - 2
4.5
Alternate Power Supply Configuration
The LXT9781 transmitter requires a current source at the center tap of the output transformer. In
the standard configuration (JP29 jumper installed) this source is supplied from the common 3.3V
power supply. However, the LXD9781 supports center-tap voltages down to 2.5V for reduced
power applications. For evaluation in a reduced-power configuration, remove JP29 and apply 2.5V
to post two of the jumper.
Developer Manual
Description
MDC. Management Data Clock. Clock for the MDIO serial channel. Maximum
frequency is 8.0 MHz.
MDIO. Management Data I/O. Bidirectional serial data channel for PHY/STA
communication.
LXD9781 PQFP Demo Board
Description
Table
8. In
13
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