Development Board Block Diagram; Handling The Board - Altera Cyclone V GT FPGA Reference Manual

1–4

Development Board Block Diagram

Figure 1–1
Figure 1–1. Cyclone V GT FPGA Development Board Block Diagram
Resistor Stuffing
Option with HSMA
Populated by Default
SDI x1
TX/RX
Transceiver x1
(Optional) )
ASSP
CPLD
SMA
Clock Output
Gigabit
Ethernet PHY
LCD
64
DDR3
SMC x64
50 MHz, 125 MHz,
and Programmable

Handling the Board

When handling the board, it is important to observe the following static discharge
precaution:
c
Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Cyclone V GT FPGA Development Board
Reference Manual
shows a block diagram of the Cyclone V GT FPGA development board.
Port A LVDS
5CGTFD9E5F35
Oscillators
x4 Edge
Port B x32 DQ/DQS
JTAG Chain
x19 USB Interface
40
4
8
8
1 Gbyte
Flash
5M2210ZF256C4N
Chapter 1: Overview
Development Board Block Diagram
Mini-USB
On-Board Version 2.0
USB-Blaster II
and USB Interface
SMA Differential
Pair Clock Input
DDR3
HMC x40
Buttons
Switches
LED
Configuration
Interface EPCQ/CvP
August 2017 Altera Corporation