Spi X4 Flash - Xilinx SP605 User Manual

Chapter 1: SP605 Evaluation Board

3. SPI x4 Flash

The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash
through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an
external SPI flash memory device.
The SP605 SPI interface has two parallel connected configuration options
SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flash
programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI
configuration source is selected via SPI select jumper J46. For details on configuring the
FPGA, see
X-Ref Target - Figure 1-3
X-Ref Target - Figure 1-4
16
"Configuration Options."
Silkscreen
Figure 1-3: J17 SPI Flash Programming Header
U32
DIN, DOUT, CCLK
SPI x4
Flash
Memory
SPIX4_CS_B
Winbond
ON = SPI X4 U32
W25Q64VSFIG
OFF = SPI EXT. J17
Figure 1-4: SPI Flash Interface Topology
www.xilinx.com
SPI Prog
J17
FPGA_PROG_B
1
FPGA_D2_MISO3
2
3 FPGA_D1_MISO2
SPI_CS_B
4
TMS
FPGA_MOSI_CSI_B_MISO0
5
TDI
FPGA_D0_DIN_MISO_MISO1
6
TDO
FPGA_CCLK
7
TCK
GND
8
GND
VCC3V3
9
3V3
HDR_1X9
U1
FPGA SPI Interface
2 1
SPI Select
Jumper
(Figure
UG526_03_092409
J17
SPI_CS_B
J46
SPI Program
Header
UG526_04_092409
SP605 Hardware User Guide
UG526 (v1.1.1) February 1, 2010
1-3): an