Sfr Definition 9.4. Psw: Program Status Word; Sfr Definition 9.5. Acc: Accumulator - Silicon Laboratories C8051F341 Product Manual

SFR Definition 9.4. PSW: Program Status Word

R/W R/W
CY AC
Bit7 Bit6
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
Bit5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1 RS0
0 0
0 1
1 0
1 1
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1: F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
R/W R/W
ACC.7 ACC.6 ACC.5
Bit7 Bit6
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
R/W R/W R/W
F0 RS1 RS0
Bit5 Bit4 Bit3
Register Bank Address
0 0x00 - 0x07
1 0x08 - 0x0F
2 0x10 - 0x17
3 0x18 - 0x1F

SFR Definition 9.5. ACC: Accumulator

R/W R/W R/W
ACC.4 ACC.3
Bit5 Bit4 Bit3
Rev. 1.3
R/W R/W R
OV F1 PARITY
Bit2 Bit1 Bit0
(bit addressable)
R/W R/W R/W
ACC.2 ACC.1 ACC.0
Bit2 Bit1 Bit0
(bit addressable)
Reset Value
00000000
SFR Address:
0xD0
Reset Value
00000000
SFR Address:
0xE0
87