Table 11.1. Reset Electrical Characteristics - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
–40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pull-Up Current
V POR Threshold (V
DD RST
Missing Clock Detector Tim-
eout
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V Monitor Turn-on Time
DD
V Monitor Supply Current
DD
106

Table 11.1. Reset Electrical Characteristics

Conditions
I = 8.5 mA, V = 2.7 to 3.6 V
OL DD
RST = 0.0 V
)
Time from last system clock ris-
ing edge to reset initiation
Delay between release of any
reset source and code execution
at location 0x0000
Rev. 1.3
Min Typ Max
0.6
0.7 x V
DD
0.3 x V
25 40
2.40 2.55 2.70
100 220 500
5.0
15
100
20 50
Units
V
V
DD
µA
V
µs
µs
µs
µs
µA