Figure 1.2. C8051F342/3/6/7 Block Diagram - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
C2D
C2CK/RST
Reset
Power-On
Reset
Supply
Monitor
VDD
Power
Net
Voltage
VREG
Regulator
GND
XTAL1
XTAL2
D+
D-
VBUS
*Low Frequency Oscillator option not available on C8051F346/7
20
Debug / Programming
Hardware
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
SFR
Bus
System Clock Setup
External
Oscillator
Clock
Multiplier
Internal
Oscillator
Clock Low Freq.
Recovery Oscillator*
USB Peripheral
Controller
Full / Low
Speed
Transceiver
1 kB RAM

Figure 1.2. C8051F342/3/6/7 Block Diagram

Rev. 1.3
Port I/O Configuration
Digital Peripherals
UART0
Timers 0, 1,
Priority
2, 3
Crossbar
Decoder
PCA/WDT
SMBus
SPI
Crossbar Control
Analog Peripherals
CP0
VREF
+
-
CP1
VDD VREF
+
-
2 Comparators
VDD
A
AIN0 - AIN20
10-bit
M
200 ksps
Temp
U
ADC
Sensor
X
P0.0
P0.1
P0.2/XTAL1
Port 0
P0.3/XTAL2
P0.4
Drivers
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
Port 1
P1.3
P1.4
Drivers
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
Port 2
P2.3
P2.4
Drivers
P2.5
P2.6
P2.7
P3.0/C2D
Port 3
Drivers