Pinout And Package Definitions; Table 4.1. Pin Definitions For The C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
4.

Pinout and Package Definitions

Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

Pin Numbers
Name
48-pin 32-pin
V 10
DD
GND 7
RST/ 13
C2CK
C2D 14
P3.0 / —
C2D
REGIN 11
VBUS 12
D+ 8
D- 9
P0.0 6
P0.1 5
P0.2 4
P0.3 3
P0.4 2
P0.5 1
P0.6 48
P0.7 47
28
Type Description
6 Power In 2.7–3.6 V Power Supply Voltage Input.
Power 3.3 V Voltage Regulator Output. See
Out
3 Ground.
9 D I/O Device Reset. Open-drain output of internal POR or V
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See
D I/O
Clock signal for the C2 Debug Interface.
— D I/O Bi-directional data signal for the C2 Debug Interface.
10 D I/O Port 3.0. See
3.
D I/O
Bi-directional data signal for the C2 Debug Interface.
7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator.
8 D In VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
4 D I/O USB D+.
5 D I/O USB D–.
2 D I/O or Port 0.0. See
A In 0.
1 D I/O or Port 0.1.
A In
32 D I/O or Port 0.2.
A In
31 D I/O or Port 0.3.
A In
30 D I/O or Port 0.4.
A In
29 D I/O or Port 0.5.
A In
28 D I/O or Port 0.6.
A In
27 D I/O or Port 0.7.
A In
Rev. 1.3
Section
Section 15 for a complete description of Port
Section 15 for a complete description of Port
8.
DD
Section 11.