Figure 1.1. C8051F340/1/4/5 Block Diagram - Silicon Laboratories C8051F341 Product Manual

C2D
Debug / Programming
C2CK/RST
Reset
Controller Core
Power-On
Reset
64/32k Byte ISP FLASH
Supply
Program Memory
Monitor
VDD
Power
Net
Voltage
VREG
Regulator
GND
System Clock Setup
XTAL1
External
XTAL2 Oscillator
Internal
Oscillator
Clock
Recovery
USB Peripheral
D+
Full / Low
D-
Speed
Transceiver
VBUS

Figure 1.1. C8051F340/1/4/5 Block Diagram

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Hardware
CIP-51 8051
256 Byte RAM
4/2k Byte XRAM
SFR
Bus
Clock
Multiplier
Low Freq.
Oscillator
Controller
1k Byte
RAM
Rev. 1.3
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0, 1,
Priority
2, 3
Crossbar
Decoder
PCA/WDT
SMBus
SPI
Crossbar Control
External Memory
Interface
P1
Control
P2 / P3
Address
P4
Data
Analog Peripherals
CP0
VREF
+
-
CP1
VDD VREF
+
-
2 Comparators
VDD
A
AIN0 - AIN19
10-bit
M
200ksps
U Temp
ADC
Sensor
X
P0.0
P0.1
P0.2
Port 0
P0.3
P0.4
Drivers
P0.5
P0.6/XTAL1
P0.7/XTAL2
P1.0
P1.1
P1.2
Port 1
P1.3
P1.4/CNVSTR
Drivers
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
Port 2
P2.3
P2.4
Drivers
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
Port 3
P3.3
Drivers P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
Port 4
P4.3
P4.4
Drivers
P4.5
P4.6
P4.7
19