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Analog Peripherals
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10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only)
Up to 200 ksps
•
Built-in analog multiplexer with single-ended and
•
differential mode
VREF from external pin, internal reference, or V
•
Built-in temperature sensor
•
External conversion start input option
•
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Two comparators
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Internal voltage reference
(C8051F340/1/2/3/4/5/6/7/A/B only)
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Brown-out detector and POR Circuitry
USB Function Controller
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USB specification 2.0 compliant
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Full speed (12 Mbps) or low speed (1.5 Mbps) operation
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Integrated clock recovery; no external crystal required for
full speed or low speed
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Supports eight flexible endpoints
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1 kB USB buffer memory
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Integrated transceiver; no external resistors required
On-Chip Debug
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On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
Provides breakpoints, single stepping,
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inspect/modify memory and registers
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Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
Voltages from 3.6 to 5.25 V supported using On-Chip
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Voltage Regulator
Rev. 1.4 9/09
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
DD
ANALOG
PERIPHERALS
+
A
10-bit
+
M
200 ksps
-
U
ADC
-
X
VREG
TEMP
VREF
SENSOR
C8051F340/1/2/34/5/6/7/A/B Only
PRECISION INTERNAL
OSCILLATORS
HIGH-SPEED CONTROLLER CORE
64/32 kB
8051 CPU
ISP FLASH
(48/25 MIPS)
FLEXIBLE
INTERRUPTS
CIRCUITRY
Copyright © 2009 by Silicon Laboratories
Full Speed USB Flash MCU Family
HIgh Speed 8051 µC Core
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Pipelined instruction architecture; executes 70% of
Instructions in 1 or 2 system clocks
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48 MIPS and 25 MIPS versions available.
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Expanded interrupt handler
Memory
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4352 or 2304 Bytes RAM
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64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
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40/25 Port I/O; All 5 V tolerant with high sink current
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Hardware enhanced SPI™, SMBus™, and one or two
enhanced UART serial ports
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Four general purpose 16-bit counter/timers
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16-bit programmable counter array (PCA) with five cap-
ture/compare modules
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External Memory Interface (EMIF)
Clock Sources
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Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
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External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
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Low Frequency (80 kHz) Internal Oscillator
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Can switch between clock sources on-the-fly
Packages
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48-pin TQFP (C8051F340/1/4/5/8/C)
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32-pin LQFP (C8051F342/3/6/7/9/A/B/D)
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5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)
Temperature Range: –40 to +85 °C
DIGITAL I/O
UART0
Port 0
UART1*
Port 1
SPI
SMBus
Port 2
PCA
Port 3
4 Timers
Port 4
48 Pin Only
* C8051F340/1/4/5/8/A/B/C Only
USB Controller /
Transceiver
4/2 kB RAM
DEBUG
POR
WDT
C8051F34x
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Table of Contents
Related Manuals for Silicon Laboratories C8051F341
Summary of Contents for Silicon Laboratories C8051F341
- Page 1 * C8051F340/1/4/5/8/A/B/C Only USB Controller / OSCILLATORS Transceiver HIGH-SPEED CONTROLLER CORE 64/32 kB 8051 CPU ISP FLASH (48/25 MIPS) FLEXIBLE DEBUG CIRCUITRY Copyright © 2009 by Silicon Laboratories Port 0 Port 1 Port 2 Port 3 Port 4 4/2 kB RAM C8051F34x...
- Page 2 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Rev. 1.4...
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Page 3: Table Of Contents
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table of Contents 1. System Overview... 17 2. Absolute Maximum Ratings ... 24 3. Global DC Electrical Characteristics ... 25 4. Pinout and Package Definitions... 28 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)... 41 5.1. Analog Multiplexer ... 42 5.2. Temperature Sensor ... 43 5.3. - Page 4 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.2.Power-Fail Reset / VDD Monitor ... 102 11.3.External Reset ... 103 11.4.Missing Clock Detector Reset ... 103 11.5.Comparator0 Reset ... 103 11.6.PCA Watchdog Timer Reset ... 103 11.7.Flash Error Reset ... 103 11.8.Software Reset ... 104 11.9.USB Reset... 104 12.
- Page 5 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.5.1.System Clock Selection ... 139 14.5.2.USB Clock Selection ... 139 15. Port Input/Output... 142 15.1.Priority Crossbar Decoder ... 144 15.2.Port I/O Initialization ... 147 15.3.General Purpose Port I/O ... 150 16. Universal Serial Bus Controller (USB0)... 159 16.1.Endpoint Addressing ... 160 16.2.USB Transceiver ...
- Page 6 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.5.3.Slave Receiver Mode ... 201 17.5.4.Slave Transmitter Mode ... 202 17.6.SMBus Status Decoding... 202 18. UART0... 205 18.1.Enhanced Baud Rate Generation... 206 18.2.Operational Modes ... 206 18.2.1.8-Bit UART ... 207 18.2.2.9-Bit UART ... 208 18.3.Multiprocessor Communications ... 208 19. UART1 (C8051F340/1/4/5/8/A/B/C Only)... 213 19.1.Baud Rate Generator ...
- Page 7 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.2.Software Timer (Compare) Mode... 259 22.2.3.High Speed Output Mode... 260 22.2.4.Frequency Output Mode ... 261 22.2.5.8-Bit Pulse Width Modulator Mode... 262 22.2.6.16-Bit Pulse Width Modulator Mode... 263 22.3.Watchdog Timer Mode ... 264 22.3.1.Watchdog Timer Operation ... 264 22.3.2.Watchdog Timer Usage ... 265 22.4.Register Descriptions for PCA...
- Page 8 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Figures 1. System Overview Figure 1.1. C8051F340/1/4/5 Block Diagram ... 19 Figure 1.2. C8051F342/3/6/7 Block Diagram ... 20 Figure 1.3. C8051F348/C Block Diagram... 21 Figure 1.4. C8051F349/D Block Diagram... 22 Figure 1.5. C8051F34A/B Block Diagram ... 23 4.
- Page 9 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12. Flash Memory Figure 12.1. Flash Program Memory Map and Security Byte... 110 13. External Data Memory Interface and On-Chip XRAM Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ... 115 Figure 13.2. Multiplexed Configuration Example... 119 Figure 13.3.
- Page 10 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 19.1. UART1 Block Diagram ... 213 Figure 19.2. UART1 Timing Without Parity or Extra Bit... 215 Figure 19.3. UART1 Timing With Parity ... 215 Figure 19.4. UART1 Timing With Extra Bit ... 215 Figure 19.5. Typical UART Interconnect Diagram... 216 Figure 19.6.
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Page 11: List Of Tables
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Tables 1. System Overview Table 1.1. Product Selection Guide ... 18 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* ... 24 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ... 25 Table 3.2. Index to Electrical Characteristics Tables ... 27 4. - Page 12 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 17.2. Minimum SDA Setup and Hold Times ... 193 Table 17.3. Sources for Hardware Changes to SMB0CN ... 197 Table 17.4. SMBus Status Decoding ... 203 18. UART0 Table 18.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ... 212 19.
- Page 13 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select ....48 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select ....49 SFR Definition 5.3.
- Page 14 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control ....134 SFR Definition 14.4. OSCXCN: External Oscillator Control ....137 SFR Definition 14.5.
- Page 15 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte ..182 USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 183 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte .
- Page 16 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte ....269 SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte ....270 C2 Register Definition 23.1.
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Page 17: System Overview
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D System Overview C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS) • In-system, full-speed, non-intrusive debug interface (on-chip) •... -
Page 18: Table 1.1. Product Selection Guide
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 1.1. Product Selection Guide C8051F340-GQ 4352 C8051F341-GQ 2304 C8051F342-GQ 4352 C8051F342-GM 4352 C8051F343-GQ 2304 C8051F343-GM 2304 C8051F344-GQ 4352 C8051F345-GQ 2304 C8051F346-GQ 4352 C8051F346-GM 4352 C8051F347-GQ 2304 C8051F347-GM 2304 C8051F348-GQ 2304 C8051F349-GQ 2304 C8051F349-GM 2304 C8051F34A-GQ 4352 C8051F34A-GM 4352... -
Page 19: Figure 1.1. C8051F340/1/4/5 Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32k Byte ISP FLASH Supply Program Memory Monitor 256 Byte RAM Power Voltage VREG 4/2k Byte XRAM Regulator System Clock Setup XTAL1 External XTAL2 Oscillator Clock Multiplier Internal Oscillator Clock... -
Page 20: Figure 1.2. C8051F342/3/6/7 Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor 256 Byte RAM Power Voltage VREG 4/2 kB XRAM Regulator System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator Clock Recovery USB Peripheral... -
Page 21: Figure 1.3. C8051F348/C Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor 256 Byte RAM Power Voltage VREG 4/2 kB XRAM Regulator System Clock Setup XTAL1 External XTAL2 Oscillator Clock Multiplier Internal Oscillator Clock... -
Page 22: Figure 1.4. C8051F349/D Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor 256 Byte RAM Power Voltage VREG 4/2 kB XRAM Regulator System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator Clock Recovery USB Peripheral... -
Page 23: Figure 1.5. C8051F34A/B Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor 256 Byte RAM Power Voltage VREG 4/2 kB XRAM Regulator System Clock Setup XTAL1 External XTAL2 Oscillator Multiplier Internal Oscillator Clock Low Freq. -
Page 24: Absolute Maximum Ratings
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND Maximum Total current through V Maximum output current sunk by RST or any Port pin *Note: Stresses above those listed under “Absolute Maximum Ratings”... -
Page 25: Global Dc Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage C8051F340/1/2/3/A/B/C/D SYSCLK (System Clock) C8051F344/5/6/7/8/9 Specified Operating Temperature Range Digital Supply Current - CPU Active (Normal Mode, accessing Flash) SYSCLK = 1 MHz, ... - Page 26 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Frequency Sensitivity T = 25 ºC T = 25 ºC T = 25 ºC T = 25 ºC Oscillator not running, Digital Supply Current (Stop Mode, shutdown) Digital Supply Current for USB...
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Page 27: Table 3.2. Index To Electrical Characteristics Tables
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Voltage Regulator Electrical Specifications Reset Electrical Characteristics Flash Electrical Characteristics AC Parameters for External Memory Interface Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics USB Transceiver Electrical Characteristics Rev. -
Page 28: Pinout And Package Definitions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Pin Numbers Name 48-pin 32-pin RST/ C2CK — P3.0 / — REGIN VBUS P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Type Description Power In 2.7–3.6 V Power Supply Voltage Input. Power 3.3 V Voltage Regulator Output. - Page 29 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued) Pin Numbers Name 48-pin 32-pin P1.0 D I/O or P1.1 D I/O or P1.2 D I/O or P1.3 D I/O or P1.4 D I/O or P1.5 D I/O or P1.6 D I/O or P1.7 D I/O or P2.0...
- Page 30 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued) Pin Numbers Name 48-pin 32-pin P3.3 — P3.4 — P3.5 — P3.6 — P3.7 — P4.0 — P4.1 — P4.2 — P4.3 — P4.4 — P4.5 — P4.6 — P4.7 — Type Description D I/O or...
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Page 31: Figure 4.1. Tqfp-48 Pinout Diagram (Top View)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.5 P0.4 P0.3 P0.2 P0.1 C8051F340/1/4/5/8/C-GQ P0.0 REGIN VBUS Figure 4.1. TQFP-48 Pinout Diagram (Top View) Top View Rev. 1.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5... -
Page 32: Figure 4.2. Tqfp-48 Package Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.2. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. 4. -
Page 33: Figure 4.3. Tqfp-48 Recommended Pcb Land Pattern
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.3. TQFP-48 Recommended PCB Land Pattern Table 4.3. TQFP-48 PCB Land Pattern Dimensions Dimension Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. -
Page 34: Figure 4.4. Lqfp-32 Pinout Diagram (Top View)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.1 P0.0 C8051F342/3/6/7/9/A/B/D-GQ REGIN VBUS Figure 4.4. LQFP-32 Pinout Diagram (Top View) Top View Rev. 1.3 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1... -
Page 35: Figure 4.5. Lqfp-32 Package Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.5. LQFP-32 Package Diagram Table 4.4. LQFP-32 Package Dimensions Dimension — 0.05 1.35 0.30 0.09 0.45 0° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. -
Page 36: Figure 4.6. Lqfp-32 Recommended Pcb Land Pattern
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.6. LQFP-32 Recommended PCB Land Pattern Table 4.5. LQFP-32 PCB Land Pattern Dimensions Dimension Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. -
Page 37: Figure 4.7. Qfn-32 Pinout Diagram (Top View)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D P0.1 P0.0 C8051F342/3/6/7/9/A/B-GM Top View REGIN GND (optional) VBUS Figure 4.7. QFN-32 Pinout Diagram (Top View) Rev. 1.3 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1... - Page 38 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.8. QFN-32 Package Drawing Table 4.6. QFN-32 Package Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation.
- Page 39 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.6. QFN-32 Package Dimensions (Continued) Dimension 0.00 — — — — Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation.
- Page 40 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 4.9. QFN-32 Recommended PCB Land Pattern Table 4.7. QFN-32 PCB Land Pattern Dimesions Dimension 4.80 4.80 0.50 BSC 0.20 Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3.
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Page 41: Bit Adc (Adc0, C8051F340/1/2/3/4/5/6/7/A/B Only)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) The ADC0 subsystem for the C8051F34x devices consists of two analog multiplexers (referred to collec- tively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configured under software control via the Special Function Registers shown in Figure 5.1. -
Page 42: Analog Multiplexer
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to individual Port pins, the on-chip temperature sensor, or the positive power supply (V input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the neg- ative input, ADC0 operates in Single-ended Mode;... -
Page 43: Temperature Sensor
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.2. Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (V ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the Offset and Slope parameters can be found in Table 5.1. TEMP Temp Figure 5.2. -
Page 44: Figure 5.3. Temperature Sensor Error With 1-Point Calibration (Vref = 2.40 V)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) 40.0 20.0 Temperature (degrees C) Rev. 1.3 60.0 80.0 -1.00 -2.00 -3.00 -4.00 -5.00... -
Page 45: Modes Of Operation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 AD0SC 31). 5.3.1. -
Page 46: Tracking Modes
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversion signal). -
Page 47: Settling Time Requirements
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu- racy required for the conversion. -
Page 48: Sfr Definition 5.1. Amx0P: Amux0 Positive Channel Select
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110... -
Page 49: Sfr Definition 5.2. Amx0N: Amux0 Negative Channel Select
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. -
Page 50: Sfr Definition 5.3. Adc0Cf: Adc0 Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.3. ADC0CF: ADC0 Configuration AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.1. -
Page 51: Sfr Definition 5.6. Adc0Cn: Adc0 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.6. ADC0CN: ADC0 Control AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: AD0TM: ADC0 Track Mode Bit. -
Page 52: Programmable Window Detector
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster sys- tem response times. -
Page 53: Sfr Definition 5.9. Adc0Lth: Adc0 Less-Than Data High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. Bit4 Bit3 Bit2... -
Page 54: Window Detector In Single-Ended Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. -
Page 55: Window Detector In Differential Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are rep- resented as 10-bit 2’s complement signed integers. -
Page 56: Table 5.1. Adc0 Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 5.1. ADC0 Electrical Characteristics = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified Parameter Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range... -
Page 57: Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) The Voltage reference MUX on C8051F34x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage V REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal refer- ence or an external source, REFSL should be set to ‘0’;... -
Page 58: Table 6.1. Voltage Reference Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 6.1. REF0CN: Reference Control Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: V used as voltage reference. -
Page 59: Comparators
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Comparators C8051F34x devices include two on-chip programmable voltage Comparators. A block diagram of the com- parators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators oper- ate identically with the following exceptions: (1) Their input selections differ, and (2) Comparator0 can be used as a reset source. -
Page 60: Figure 7.1. Comparator Functional Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D CPnEN CPnOUT CPnRIF CPnFIF CMXnN2 CPnHYP1 CMXnN1 CPnHYP0 CMXnN0 CPnHYN1 CPnHYN0 CMXnP2 CMXnP1 CMXnP0 Port I/O connection options vary with package (32-pin or 48-pin) Figure 7.1. Comparator Functional Block Diagram Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock;... -
Page 61: Figure 7.2. Comparator Hysteresis Plot
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D CP0+ VIN+ CP0- VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ OUTPUT Positive Hysteresis Disabled Figure 7.2. Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. -
Page 62: Sfr Definition 7.1. Cpt0Cn: Comparator0 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.1. CPT0CN: Comparator0 Control CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. -
Page 63: Sfr Definition 7.2. Cpt0Mx: Comparator0 Mux Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection CMX0N2 CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX0N2–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N1 CMX0N1 CMX0N0 Bit3: UNUSED. -
Page 64: Sfr Definition 7.3. Cpt0Md: Comparator0 Mode Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 falling-edge interrupt disabled. -
Page 65: Sfr Definition 7.4. Cpt1Cn: Comparator1 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.4. CPT1CN: Comparator1 Control CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage on CP1+ > CP1–. Bit5: CP1RIF: Comparator1 Rising-Edge Flag. -
Page 66: Sfr Definition 7.5. Cpt1Mx: Comparator1 Mux Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection CMX1N2 CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. CMX1N2 CMX1N1 CMX1N0 Bit3: UNUSED. -
Page 67: Sfr Definition 7.6. Cpt1Md: Comparator1 Mode Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection CP1RIE CP1FIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt enabled. Bit4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 falling-edge interrupt disabled. -
Page 68: Table 7.1. Comparator Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 7.1. Comparator Electrical Characteristics = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter CP0+ – CP0– = 100 mV Response Time: Mode 0, Vcm* = 1.5 V CP0+ –... -
Page 69: Voltage Regulator (Reg0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Voltage Regulator (REG0) C8051F34x devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. -
Page 70: Figure 8.1. Reg0 Configuration: Usb Bus-Powered
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D VBUS From VBUS REGIN To 3 V Power Net Figure 8.1. REG0 Configuration: USB Bus-Powered VBUS From VBUS From 5 V REGIN Power Net To 3 V Power Net Figure 8.2. REG0 Configuration: USB Self-Powered VBUS Sense 5 V In Voltage Regulator (REG0) 3 V Out VBUS Sense... -
Page 71: Figure 8.3. Reg0 Configuration: Usb Self-Powered, Regulator Disabled
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D VBUS From VBUS VBUS Sense REGIN 5 V In Voltage Regulator (REG0) 3 V Out From 3 V Device Power Net Power Net Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled VBUS VBUS Sense From 5 V REGIN 5 V In Voltage Regulator (REG0) Power Net 3 V Out... -
Page 72: Sfr Definition 8.1. Reg0Cn: Voltage Regulator Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 8.1. REG0CN: Voltage Regulator Control REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently present (device attached to USB network). -
Page 73: Microcontroller
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 18), an Enhanced SPI (see description in... -
Page 74: Instruction Set
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. -
Page 75: Movx Instruction And Program Memory
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.1.2. MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip data XRAM (only on C8051F340/1/4/5/8 devices), and accessing on-chip program Flash memory. The Flash access feature provides a mechanism for user software to update program code and use the pro- gram memory space for non-volatile data storage (see External Memory Interface (only on C8051F340/1/4/5/8 devices) provides a fast access interface to off-chip data XRAM (or memory-mapped peripherals) via the MOVX instruction. - Page 76 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ORL A, #data OR immediate to A ORL direct, A OR A to direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A...
- Page 77 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit...
- Page 78 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps.
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Page 79: Memory Organization
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 9.2 and Figure 9.3. -
Page 80: Program Memory
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D PROGRAM/DATA MEMORY (FLASH) 0x7FFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 9.3. On-Chip Memory Map for 32 kB Devices 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F34x implements 64k or 32k bytes of this program memory space as in-system, re-programmable Flash memory. -
Page 81: Data Memory
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. -
Page 82: Special Function Registers
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. -
Page 83: Table 9.3. Special Function Registers
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High... - Page 84 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description P1MDIN 0xF2 Port 1 Input Mode Configuration P1MDOUT 0xA5 Port 1 Output Mode Configuration P1SKIP 0xD5 Port 1 Skip 0xA0 Port 2 Latch P2MDIN...
- Page 85 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description SBUF0 0x99 UART0 Data Buffer SCON0 0x98 UART0 Control SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 SMBus Data SMOD1...
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Page 86: Register Descriptions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. -
Page 87: Sfr Definition 9.4. Psw: Program Status Word
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.4. PSW: Program Status Word Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow... -
Page 88: Interrupt Handler
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.6. B: B Register Bit7 Bit6 Bit5 Bits7–0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority levels. -
Page 89: Interrupt Priorities
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D IN0PL INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.13). Note that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. -
Page 90: Interrupt Register Descriptions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B USB0 0x0043 ADC0 Window 0x004B... -
Page 91: Sfr Definition 9.7. Ie: Interrupt Enable
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.7. IE: Interrupt Enable ESPI0 Bit7 Bit6 Bit5 Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. Bit6: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. -
Page 92: Sfr Definition 9.8. Ip: Interrupt Priority
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.8. IP: Interrupt Priority PSPI0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. -
Page 93: Sfr Definition 9.9. Eie1: Extended Interrupt Enable 1
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. Bit6: ECP1: Enable Comparator1 (CP1) Interrupt. -
Page 94: Sfr Definition 9.10. Eip1: Extended Interrupt Priority 1
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. -
Page 95: Sfr Definition 9.12. Eip2: Extended Interrupt Priority 2
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 Bit7 Bit6 Bit5 Bits7–2: UNUSED. Read = 000000b. Write = don’t care. Bit1: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. Bit0: EVBUS: Enable VBUS Level Interrupt. -
Page 96: Sfr Definition 9.13. It01Cf: Int0/Int1 Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.13. IT01CF: INT0/INT1 Configuration IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: INT1 Polarity 0: INT1 input is active low. 1: INT1 input is active high. Bits6–4: IN1SL2–0: INT1 Port Pin Selection Bits These bits select which Port pin is assigned to INT1. -
Page 97: Power Management Modes
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). -
Page 98: Sfr Definition 9.14. Pcon: Power Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 9.14. PCON: Power Control Bit7 Bit6 Bit5 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). -
Page 99: Prefetch Engine
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 10. Prefetch Engine The 48 MHz versions of the C8051F34x family of devices incorporate a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. -
Page 100: Reset Sources
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their defined reset values •... -
Page 101: Power-On Reset
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until V . A Power-On Reset delay (T PORDelay typically less than 0.3 ms. Figure 11.2. plots the power-on and V On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. -
Page 102: Power-Fail Reset / Vdd Monitor
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.2. Power-Fail Reset / V When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When V to a level above V , the CIP-51 will be released from the reset state. -
Page 103: External Reset
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the RST pin generates a reset; an external pull-up and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. -
Page 104: Software Reset
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 11.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the RST pin is unaffected by this reset. 11.9. -
Page 105: Sfr Definition 11.2. Rstsrc: Reset Source
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 11.2. RSTSRC: Reset Source USBRSF FERROR C0RSEF SWRSF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. Bit6: FERROR: Flash Error Indicator. -
Page 106: Table 11.1. Reset Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 11.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter = 8.5 mA, V RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pull-Up Current RST = 0.0 V POR Threshold (V Missing Clock Detector Tim- Time from last system clock ris- eout... -
Page 107: Flash Memory
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. -
Page 108: Flash Write Procedure
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 12.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. -
Page 109: Non-Volatile Data Storage
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 12.1. Flash Electrical Characteristics Parameter C8051F340/2/4/6/A/C/D* Flash Size C8051F341/3/5/7/8/9/B Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 1024 bytes at location 0xFC00 to 0xFFFF are reserved. 12.2. Non-Volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. -
Page 110: Figure 12.1. Flash Program Memory Map And Security Byte
Figure 12.1. Flash Program Memory Map and Security Byte 0xFC00 0xFBFF Locked when any 0xFBFE other FLASH pages are locked 0xFA00 C8051F341/3/5/7/8/9/B Unlocked FLASH Pages Access limit set according to the FLASH security lock byte 0x0000 Rev. 1.3 Lock Byte... - Page 111 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The level of FLASH security depends on the FLASH access method. The three FLASH access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Accessing FLASH from the C2 debug interface: 1.
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Page 112: Sfr Definition 12.1. Psctl: Program Store R/W Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 12.1. PSCTL: Program Store R/W Control Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased. -
Page 113: Sfr Definition 12.3. Flscl: Flash Scale
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 12.3. FLSCL: Flash Scale FOSE Reserved Reserved Bit7 Bit6 Bit5 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen- cies below 10 MHz, disabling the Flash one-shot will increase system power consumption. -
Page 114: External Data Memory Interface And On-Chip Xram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13. External Data Memory Interface and On-Chip XRAM 4k Bytes (C8051F340/2/4/6/A/C/D) or 2k Bytes (C8051F341/3/5/7/8/9/B) of RAM are included on-chip, and mapped into the external data memory space (XRAM). The 1k Bytes of USB FIFO space can also be mapped into XRAM address space for additional general-purpose data storage. -
Page 115: Accessing Usb Fifo Space
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.2. Accessing USB FIFO Space The C8051F34x devices include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO regis- ters;... -
Page 116: Configuring The External Memory Interface
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.3. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. -
Page 117: Sfr Definition 13.1. Emi0Cn: External Memory Interface Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 13.1. EMI0CN: External Memory Interface Control Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xAA Bits7–0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. -
Page 118: Sfr Definition 13.2. Emi0Cf: External Memory Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 13.2. EMI0CF: External Memory Configuration USBFAE Bit7 Bit6 Bit5 Bit7: Unused. Read = 0b. Write = don’t care. Bit6: USBFAE: USB FIFO Access Enable. 0: USB FIFO RAM not available through MOVX instructions. 1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be mapped in XRAM space at addresses 0x0400 to 0x07FF. -
Page 119: Multiplexed And Non-Multiplexed Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.5. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 13.5.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. -
Page 120: Non-Multiplexed Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.5.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 13.3. See page 124 for more information about Non-multiplexed operation. A[15:0] D[7:0] Figure 13.3. -
Page 121: Internal Xram Only
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.6.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space. -
Page 122: Split Mode With Bank Select
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.6.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. •... -
Page 123: Sfr Definition 13.3. Emi0Tc: External Memory Timing Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 13.3. EMI0TC: External Memory Timing Control EAS1 EAS0 EWR3 Bit7 Bit6 Bit5 Bits7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. -
Page 124: Non-Multiplexed Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1. Non-multiplexed Mode 13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] ADDR[7:0] DATA[7:0] P1.7 P1.6 ADDR[15:8] ADDR[7:0] DATA[7:0] P1.6 P1.7 Figure 13.5. Non-multiplexed 16-bit MOVX Timing Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL EMIF WRITE DATA Nonmuxed 16-bit READ EMIF ADDRESS (8 MSBs) from DPH... -
Page 125: Figure 13.6. Non-Multiplexed 8-Bit Movx Without Bank Select Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. ADDR[15:8] ADDR[7:0] DATA[7:0] P1.7 P1.6 ADDR[15:8] ADDR[7:0] DATA[7:0] P1.6 P1.7 Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing Nonmuxed 8-bit WRITE without Bank Select EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF WRITE DATA Nonmuxed 8-bit READ without Bank Select EMIF ADDRESS (8 LSBs) from R0 or R1... -
Page 126: Figure 13.7. Non-Multiplexed 8-Bit Movx With Bank Select Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.7 P1.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.6 P1.7 Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing Muxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN EMIF WRITE DATA... -
Page 127: Multiplexed Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] ALEH P1.3 P1.7 P1.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] ALEH P1.3 P1.6 P1.7 Figure 13.8. Multiplexed 16-bit MOVX Timing Muxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF WRITE DATA... -
Page 128: Figure 13.9. Multiplexed 8-Bit Movx Without Bank Select Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.7 P1.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.6 P1.7 Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing Muxed 8-bit WRITE Without Bank Select EMIF WRITE DATA ALEL... -
Page 129: Figure 13.10. Multiplexed 8-Bit Movx With Bank Select Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.7 P1.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] R0 or R1 ALEH P1.3 P1.6 P1.7 Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing Muxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN EMIF WRITE DATA... -
Page 130: Table 13.1. Ac Parameters For External Memory Interface
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 13.1. AC Parameters for External Memory Interface Parameter Description Address / Control Setup Time Address / Control Pulse Width Address / Control Hold Time Address Latch Enable High Time ALEH Address Latch Enable Low Time ALEL Write Data Setup Time Write Data Hold Time Read Data Setup Time Read Data Hold Time... -
Page 131: Oscillators
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14. Oscillators C8051F34x devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator (C8051F340/1/2/3/4/5/8/9/A/B/C/D), an external oscillator drive circuit, and a 4x Clock Multiplier. The internal high-frequency and low-frequency oscillators can be enabled/disabled and adjusted using the special function registers, as shown in Figure 14.1. The system clock (SYSCLK) can be derived from either of the internal oscillators, the external oscillator circuit, or the 4x Clock Multiplier divided by 2. -
Page 132: Programmable Internal High-Frequency (H-F) Oscillator
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.1. Programmable Internal High-Frequency (H-F) Oscillator All C8051F34x devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register shown in SFR Definition 14.2. The OSCICL register is factory calibrated to obtain a 12 MHz internal oscillator frequency. Electrical specifications for the precision internal oscillator are given in Table 14.1 on page 141. -
Page 133: Programmable Internal Low-Frequency (L-F) Oscillator
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration Bit7 Bit6 Bit5 Bits4–0: OSCCAL: Oscillator Calibration Value These bits determine the internal H-F oscillator period. When set to 00000b, the oscillator operates at its fastest setting. When set to 11111b, the oscillator operates at is slowest set- ting. -
Page 134: Sfr Definition 14.3. Osclcn: Internal L-F Oscillator Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control OSCLEN OSCLRDY OSCLF3 Bit7 Bit6 Bit5 Bit7: OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSCLRDY: Internal L-F Oscillator Ready Flag. 0: Internal L-F Oscillator frequency not stabilized. 1: Internal L-F Oscillator frequency stabilized. -
Page 135: External Oscillator Drive Circuit
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/ resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. A 10 M resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. -
Page 136: External Rc Example
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.3.3. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. -
Page 137: Sfr Definition 14.4. Oscxcn: External Oscillator Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 14.4. OSCXCN: External Oscillator Control XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6–4: XOSCMD2–0: External Oscillator Mode Bits. -
Page 138: Clock Multiplier
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.4. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “16.4. USB Clock Configuration” on page 166 the Multiplier output can also be used as the system clock. C8051F340/1/2/3 devices can use the 48 MHz Clock Multiplier output as system clock. -
Page 139: System And Usb Clock Selection
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 14.5. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immedi- ately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resona- tors typically require a start-up time before they are settled and ready for use. -
Page 140: Sfr Definition 14.6. Clksel: Clock Select
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Internal Oscillator Clock Signal Input Source Selection USB Clock External Oscillator / 4 Crystal Oscillator Mode External Oscillator 24 MHz Crystal SFR Definition 14.6. CLKSEL: Clock Select USBCLK Bit7 Bit6 Bit5 Bit 7: Unused. Read = 0b; Write = don’t care. Bits6–4: USBCLK2–0: USB Clock Select These bits select the clock supplied to USB0. -
Page 141: Table 14.1. Oscillator Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 14.1. Oscillator Electrical Characteristics = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b Oscillator Supply Current 24 ºC, V (from V OSCICN.7 = 1 Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency OSCLD = 11b... -
Page 142: Port Input/Output
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15. Port Input/Output Digital and analog resources are available through 40 I/O pins (48-pin packages) or 25 I/O pins (32-pin packages). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as gen- eral-purpose I/O (GPIO) or analog input;... -
Page 143: Figure 15.2. Port I/O Cell Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D W E A K -P U LLU P P U S H -P U LL P O R T -O U T E N A B LE P O R T -O U T P U T A nalog S elect A N A LO G IN P U T P O R T -IN P U T Figure 15.2. -
Page 144: Priority Crossbar Decoder
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. -
Page 145: Figure 15.4. Crossbar Priority Decoder In Example Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SF Signals (32-pin Package) SF Signals (48-pin Package) PIN I/O MISO MOSI NSS* *NSS is only pinned out in 4-wire SPI mode CP0A CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 TX1** RX1** P0SKIP[0:7] Port pin assigned to peripheral by the Crossbar SF Signals Special Function Signals are not assigned by the Crossbar. -
Page 146: Figure 15.5. Crossbar Priority Decoder In Example Configuration (3 Pins Skipped)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D S F Signa ls (32-pin P a cka ge ) S F Signa ls (48-pin P a cka ge ) P IN I/O TX 0 S CK M ISO M OSI NSS* S DA S CL CP0A CP1A S YSCLK CEX0 CEX1 CEX2... -
Page 147: Port I/O Initialization
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). -
Page 148: Sfr Definition 15.1. Xbr0: Port I/O Crossbar Register 0
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. -
Page 149: Sfr Definition 15.2. Xbr1: Port I/O Crossbar Register 1
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 WEAKPUD XBARE Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. -
Page 150: General Purpose Port I/O
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 15.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. Port 4 (48-pin packages only) uses an SFR which is byte-addressable. -
Page 151: Sfr Definition 15.6. P0Mdout: Port0 Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.6. P0MDOUT: Port0 Output Mode Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT). -
Page 152: Sfr Definition 15.10. P1Mdout: Port1 Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.8. P1: Port1 Latch P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’... -
Page 153: Sfr Definition 15.13. P2Mdin: Port2 Input Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.11. P1SKIP: Port1 Skip Bit7 Bit6 Bit5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. -
Page 154: Sfr Definition 15.14. P2Mdout: Port2 Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.14. P2MDOUT: Port2 Output Mode Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis- ter P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. SFR Definition 15.15. -
Page 155: Sfr Definition 15.18. P3Mdout: Port3 Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.16. P3: Port3 Latch P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. -
Page 156: Sfr Definition 15.19. P3Skip: Port3 Skip
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.19. P3SKIP: Port3 Skip Bit7 Bit6 Bit5 Bits7–0: P3SKIP[3:0]: Port3 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. -
Page 157: Sfr Definition 15.22. P4Mdout: Port4 Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 15.21. P4MDIN: Port4 Input Mode Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P4.7–P4.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P4.n pin is configured as an analog input. 1: Corresponding P4.n pin is not configured as an analog input. -
Page 158: Table 15.1. Port I/O Dc Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 15.1. Port I/O DC Electrical Characteristics = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified Parameters = –3 mA, Port I/O push-pull = –10 µA, Port I/O push-pull Output High Voltage = –10 mA, Port I/O push-pull = 8.5 mA = 10 µA Output Low Voltage... -
Page 159: Universal Serial Bus Controller (Usb0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16. Universal Serial Bus Controller (USB0) C8051F34x devices include a complete Full/Low Speed USB function for USB peripheral implementa- tions*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mech- anism for crystal-less operation. -
Page 160: Endpoint Addressing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 16.1. Endpoint Addressing Scheme Endpoint Associated Pipes Endpoint0... -
Page 161: Sfr Definition 16.1. Usb0Xcn: Usb0 Transceiver Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.1. USB0XCN: USB0 Transceiver Control PREN PHYEN SPEED PHYTST1 PHYTST0 DFREC Bit7 Bit6 Bit5 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from the USB network). 1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB net- work). -
Page 162: Usb Register Access
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.3. USB Register Access The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 16.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end- point number. -
Page 163: Sfr Definition 16.2. Usb0Adr: Usb0 Indirect Address
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.2. USB0ADR: USB0 Indirect Address BUSY AUTORD Bit7 Bit6 Bit5 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The target address and BUSY bit may be written in the same write to USB0ADR. -
Page 164: Sfr Definition 16.3. Usb0Dat: Usb0 Data
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 16.3. USB0DAT: USB0 Data Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. -
Page 165: Table 16.2. Usb0 Controller Registers
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 16.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F FIFOn 0x20–0x23 E0CSR 0x11 EINCSRL EINCSRH 0x12... -
Page 166: Usb Clock Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “14. -
Page 167: Fifo Management
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.5. FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 16.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT). 0x07FF Endpoint0 (64 bytes) -
Page 168: Usb Register Definition 16.6. Fifon: Usb0 Endpoint Fifo Access
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. -
Page 169: Function Addressing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). - Page 170 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D “14. Oscillators” on page 131 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener- ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscil- lator will exit Suspend mode upon any of the above listed events.
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Page 171: Usb Register Definition 16.8. Power: Usb0 Power
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.8. POWER: USB0 Power ISOUD USBINH Bit7 Bit6 Bit5 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is received. -
Page 172: Interrupts
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 16.10. FRAMEH: USB0 Frame Number High Bit7 Bit6 Bit5 Bits7-3: Unused. -
Page 173: Usb Register Definition 16.12. Out1Int: Usb0 Out Endpoint Interrupt
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active. -
Page 174: Usb Register Definition 16.13. Cmint: Usb0 Common Interrupt
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.13. CMINT: USB0 Common Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hard- ware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted. -
Page 175: Usb Register Definition 16.15. Out1Ie: Usb0 Out Endpoint Interrupt Enable
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. Bit2: IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled. -
Page 176: The Serial Interface Engine
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF interrupt enabled. Bit2: RSTINTE: Reset Interrupt Enable 0: Reset interrupt disabled. -
Page 177: Endpoint0 Setup Transactions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’... -
Page 178: Endpoint0 Out Transactions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 16.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to ‘1’... -
Page 179: Usb Register Definition 16.17. E0Csr: Usb0 Endpoint0 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control SSUEND SOPRDY SDSTL SUEND DATAEND Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. Read: This bit always reads ‘0’. -
Page 180: Configuring Endpoints1-3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’. -
Page 181: Endpoints1-3 In Isochronous Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. -
Page 182: Usb Register Definition 16.19. Eincsrl: Usb0 In Endpoint Control Low Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. -
Page 183: Controlling Endpoints1-3 Out
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte DBIEN DIRSEL Bit7 Bit6 Bit5 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. Bit6: ISO: Isochronous Transfer Enable. -
Page 184: Endpoints1-3 Out Isochronous Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen- erates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must be reset to ‘0’... -
Page 185: Endpoint Control Low Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte CLRDT STSTL SDSTL Bit7 Bit6 Bit5 Bit7: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’. Read: This bit always reads ‘0’. -
Page 186: Usb Register Definition 16.24. Eoutcnth: Usb0 Out Endpoint Count High
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte DBOEN Bit7 Bit6 Bit5 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. Bit6: ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint. -
Page 187: Table 16.4. Usb Transceiver Electrical Characteristics
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 16.4. USB Transceiver Electrical Characteristics = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified Parameters Symbol Transmitter Output High Voltage Output Low Voltage Output Crossover Point Output Impedance Pull-up Resistance Output Rise Time Output Fall Time Receiver Differential Input Sensitivity... -
Page 188: Smbus
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. -
Page 189: Supporting Documents
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. -
Page 190: Arbitration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. -
Page 191: Clock Low Extension
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. -
Page 192: Smbus Configuration Register
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SMBus configuration options include: • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) • SDA setup and hold time extensions • Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in tion Register”... -
Page 193: Figure 17.4. Typical Smbus Scl Generation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 17.4 shows the typical SCL generation described by Equation 17.2. Notice that T twice as large as T . The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 17.1. -
Page 194: Sfr Definition 17.1. Smb0Cf: Smbus Clock/Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration ENSMB BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. Bit6: INH: SMBus Slave Inhibit. -
Page 195: Smb0Cn Control Register
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 17.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. -
Page 196: Sfr Definition 17.2. Smb0Cn: Smbus Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 17.2. SMB0CN: SMBus Control MASTER TXMODE Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. -
Page 197: Table 17.3. Sources For Hardware Changes To Smb0Cn
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 17.3. Sources for Hardware Changes to SMB0CN Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by an address byte is received. -
Page 198: Data Register
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. -
Page 199: Figure 17.5. Typical Master Transmitter Sequence
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Data Byte Interrupt Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 17.5. Typical Master Transmitter Sequence Rev. 1.3 Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address... -
Page 200: Master Receiver Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. -
Page 201: Slave Receiver Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. -
Page 202: Slave Transmitter Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 17.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. -
Page 203: Table 17.4. Smbus Status Decoding
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 17.4. SMBus Status Decoding Values Read Current SMbus State 1110 X A master START was generated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte was transmitted; ACK received. A master data byte was received; 1000 ACK requested. - Page 204 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 17.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave byte was transmitted; NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted; error detected. An illegal STOP or bus error was 0101 detected while a Slave Transmis- sion was in progress.
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Page 205: Uart0
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 18. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details Section “18.1. Enhanced Baud Rate Generation” on page 206 UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. -
Page 206: Enhanced Baud Rate Generation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 18.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 18.2), which is not user-accessible. -
Page 207: 8-Bit Uart
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 18.3. UART Interconnect Diagram 18.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). -
Page 208: 9-Bit Uart
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 18.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. -
Page 209: Figure 18.6. Uart Multi-Processor Mode Interconnect Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Master Slave Slave Slave Device Device Device Device Figure 18.6. UART Multi-Processor Mode Interconnect Diagram Rev. 1.3... -
Page 210: Sfr Definition 18.1. Scon0: Serial Port 0 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 18.1. SCON0: Serial Port 0 Control S0MODE MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. -
Page 211: Sfr Definition 18.2. Sbuf0: Serial (Uart0) Port Data Buffer
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x99 SFR Address: Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. -
Page 212: Table 18.1. Timer Settings For Standard Baud Rates Using The Internal Oscillator
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 18.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Actual Baud Baud Baud Rate Error Rate (bps) Rate (bps) 230400 230769 0.16% 115200 115385 0.16% 57600 57692 0.16% 28800 28846 0.16% 14400 14423 0.16% 9600 9615 0.16% 2400... -
Page 213: Uart1 (C8051F340/1/4/5/8/A/B/C Only)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 19. UART1 (C8051F340/1/4/5/8/A/B/C Only) UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in Section “19.1. -
Page 214: Baud Rate Generator
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 19.1. Baud Rate Generator The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock (SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK frequencies. -
Page 215: Data Format
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 19.2. Data Format UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). -
Page 216: Configuration And Operation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 19.3. Configuration and Operation UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. To operate in a point-to-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be cleared to ‘0’. -
Page 217: Multiprocessor Communications
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1 is set. RI1 can only be cleared to '0' by software when there is no more information in the FIFO. The rec- ommended procedure to empty the FIFO contents is as follows: 1. -
Page 218: Figure 19.6. Uart Multi-Processor Mode Interconnect Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Figure 19.6. UART Multi-Processor Mode Interconnect Diagram SFR Definition 19.1. SCON1: UART1 Control OVR1 PERR1 THRE1 Bit7 Bit6 Bit5 Bit7: OVR1: Receive FIFO Overrun Flag. This bit is used to indicate a receive FIFO overrun condition. 0: Receive FIFO Overrun has not occurred. 1: Receive FIFO Overrun has occurred (an incoming character was discarded due to a full FIFO). -
Page 219: Sfr Definition 19.2. Smod1: Uart1 Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 19.2. SMOD1: UART1 Mode MCE1 S1PT1 S1PT0 Bit7 Bit6 Bit5 Bit7: MCE1: Multiprocessor Communication Enable. 0: RI will be activated if stop bit(s) are ‘1’. 1: RI will be activated if stop bit(s) and extra bit are ‘1’ (extra bit must be enabled using XBE1). -
Page 220: Sfr Definition 19.4. Sbcon1: Uart1 Baud Rate Generator Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 19.3. SBUF1: UART1 Data Buffer Bit7 Bit6 Bit5 Bits7–0: SBUF1[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR is used to both send data from the UART and to read received data from the UART1 receive FIFO. Write: Writing a byte to SBUF1 initiates the transmission. -
Page 221: Sfr Definition 19.5. Sbrlh1: Uart1 Baud Rate Generator High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte Bit7 Bit6 Bit5 Bits7–0: SBRLH1[7:0]: High Byte of reload value for UART1 Baud Rate Generator. SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte Bit7 Bit6 Bit5 Bits7–0: SBRLL1[7:0]: Low Byte of reload value for UART1 Baud Rate Generator. Bit4 Bit3 Bit2... -
Page 222: Enhanced Serial Peripheral Interface (Spi0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single SPI bus. -
Page 223: Signal Descriptions
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 20.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. -
Page 224: Spi0 Master Mode Operation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CFG.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. -
Page 225: Figure 20.2. Multiple-Master Mode Connection Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Master Device 1 Figure 20.2. Multiple-Master Mode Connection Diagram Master Device Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram GPIO MISO MISO Master MOSI MOSI Device 2... -
Page 226: Spi0 Slave Mode Operation
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal. -
Page 227: Serial Clock Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. -
Page 228: Figure 20.6. Slave Mode Data/Clock Timing (Ckpha = 0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (CKPOL=0, CKPHA=0) (CKPOL=1, CKPHA=0) MOSI MISO NSS (4-Wire Mode) Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) (CKPOL=0, CKPHA=1) (CKPOL=1, CKPHA=1) MOSI MISO NSS (4-Wire Mode) Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 6... -
Page 229: Spi Special Function Registers
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 20.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. -
Page 230: Sfr Definition 20.2. Spi0Cn: Spi0 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 20.2. SPI0CN: SPI0 Control SPIF WCOL MODF Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. -
Page 231: Sfr Definition 20.3. Spi0Ckr: Spi0 Clock Rate
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. -
Page 232: Figure 20.8. Spi Master Timing (Ckpha = 0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SCK* MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.8. SPI Master Timing (CKPHA = 0) SCK* MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.9. -
Page 233: Figure 20.10. Spi Slave Timing (Ckpha = 0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.10. SPI Slave Timing (CKPHA = 0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.11. -
Page 234: Table 20.1. Spi Slave Timing Parameters
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 20.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing* (See Figure 20.8 and Figure 20.9) SCK High Time MCKH SCK Low Time MCKL MISO Valid to SCK Shift Edge SCK Shift Edge to MISO Change Slave Mode Timing* (See Figure 20.10 and Figure 20.11) NSS Falling to First SCK Edge Last SCK Edge to NSS Rising NSS Falling to MISO Valid... -
Page 235: Timers
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, USB (frame measure- ments), Low-Frequency Oscillator (period measurements), or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. -
Page 236: Mode 1: 16-Bit Counter/Timer
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “15.1. Priority Crossbar Decoder” on page 144 pins). -
Page 237: Mode 2: 8-Bit Counter/Timer With Auto-Reload
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. -
Page 238: Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/ timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. -
Page 239: Sfr Definition 21.1. Tcon: Timer Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.1. TCON: Timer Control Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow detected. -
Page 240: Sfr Definition 21.2. Tmod: Timer Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.2. TMOD: Timer Mode GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in register INT01CF (see SFR Definition 9.13). -
Page 241: Sfr Definition 21.3. Ckcon: Clock Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.3. CKCON: Clock Control T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8-bit timer mode. -
Page 242: Sfr Definition 21.6. Th0: Timer 0 High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.4. TL0: Timer 0 Low Byte Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 21.5. TL1: Timer 1 Low Byte Bit7 Bit6 Bit5 Bits 7–0: TL1: Timer 1 Low Byte. -
Page 243: Timer 2
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3), T2CE (TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits. -
Page 244: 8-Bit Timers With Auto-Reload
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.2.2. 8-bit Timers with Auto-Reload When T2SPLIT = ‘1’ and T2CE = ‘0’, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. -
Page 245: Timer 2 Capture Modes: Usb Start-Of-Frame Or Lfo Falling Edge
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge When T2CE = ‘1’, Timer 2 will operate in one of two special capture modes. The capture event can be selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling Edge capture, using the T2CSS bit. -
Page 246: Figure 21.7. Timer 2 Capture Mode (T2Split = '1')
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con- tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A Timer 2 interrupt is generated if enabled. -
Page 247: Sfr Definition 21.8. Tmr2Cn: Timer 2 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.8. TMR2CN: Timer 2 Control TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. -
Page 248: Sfr Definition 21.10. Tmr2Rlh: Timer 2 Reload Register High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit7 Bit6 Bit5 Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2 when operating in auto-reload mode, or the captured value of the TMR2L register in capture mode. SFR Definition 21.10. -
Page 249: Timer 3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture mode, or Low-Frequency Oscillator (LFO) Rising Edge capture mode. The Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3), T3CE (TMR3CN.4) bits, and T3CSS (TMR3CN.1) bits. -
Page 250: 8-Bit Timers With Auto-Reload
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is ‘1’ and T3CE = ‘0’, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. -
Page 251: Usb Start-Of-Frame Capture
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 21.3.3. USB Start-of-Frame Capture When T3CE = ‘1’, Timer 3 will operate in one of two special capture modes. The capture event can be selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Rising Edge capture, using the T3CSS bit. The USB SOF capture mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock. -
Page 252: Figure 21.11. Timer 3 Capture Mode (T3Split = '1')
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con- tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A Timer 3 interrupt is generated if enabled. -
Page 253: Sfr Definition 21.13. Tmr3Cn: Timer 3 Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.13. TMR3CN: Timer 3 Control TF3H TF3L TF3LEN Bit7 Bit6 Bit5 Bit7: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. -
Page 254: Sfr Definition 21.15. Tmr3Rlh: Timer 3 Reload Register High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit7 Bit6 Bit5 Bits 7–0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3 when operating in auto-reload mode, or the captured value of the TMR3L register when operating in capture mode. SFR Definition 21.15. -
Page 255: Programmable Counter Array (Pca0)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22. Programmable Counter Array (PCA0) The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Crossbar Decoder”... -
Page 256: Pca Counter/Timer
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. -
Page 257: Capture/Compare Modules
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. -
Page 258: Edge-Triggered Capture Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). -
Page 259: Software Timer (Compare) Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. -
Page 260: High Speed Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode. -
Page 261: Frequency Output Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave is then defined by Equation 22.1. Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation. -
Page 262: 8-Bit Pulse Width Modulator Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. -
Page 263: 16-Bit Pulse Width Modulator Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high;... -
Page 264: Watchdog Timer Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified limit. -
Page 265: Watchdog Timer Usage
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Offset Equation 22.4. Watchdog Timer Offset in PCA Clocks The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is enabled. -
Page 266: Register Descriptions For Pca
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 22.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 22.1. PCA0CN: PCA Control Bit7 Bit6 Bit5 Bit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. -
Page 267: Sfr Definition 22.2. Pca0Md: Pca Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.2. PCA0MD: PCA Mode CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. -
Page 268: Sfr Definition 22.3. Pca0Cpmn: Pca Capture/Compare Mode
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode PWM16n ECOMn CAPPn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA (n = 0), PCA0CPM1 = 0xDB (n = 1), PCA0CPM2 = 0xDC (n = 2), PCA0CPM3 = 0xDD (n = 3), PCA0CPM4 = 0xDE (n = 4) Bit7: PWM16n: 16-bit Pulse Width Modulation Enable. -
Page 269: Sfr Definition 22.5. Pca0H: Pca Counter/Timer High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte Bit7 Bit6 Bit5 Bits 7–0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte Bit7 Bit6 Bit5... -
Page 270: Sfr Definition 22.7. Pca0Cphn: Pca Capture Module High Byte
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte Bit7 Bit6 Bit5 PCA0CPHn Address: PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0xEA (n = 1), PCA0CPH2 = 0xEC (n = 2), PCA0CPH3 = 0xEE (n = 3), PCA0CPH4 = 0xFE (n = 4) Bits7–0: PCA0CPHn: PCA Capture Module High Byte. -
Page 271: C2 Interface
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 23. C2 Interface C8051F34x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash program- ming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. -
Page 272: C2 Register Definition 23.4. Fpctl: C2 Flash Programming Control
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D C2 Register Definition 23.3. REVID: C2 Revision ID Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID. C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control Bit7 Bit6 Bit5 Bits7–0 FPCTL: Flash Programming Control Register. This register is used to enable Flash programming via the C2 interface. To enable C2 Flash programming, the following codes must be written in order: 0x02, 0x01. -
Page 273: C2 Pin Sharing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 23.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming functions may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely ‘borrow’... -
Page 274: Document Change List
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D OCUMENT HANGE Revision 0.5 to Revision 1.0 • Updated Table 3.1, “Global DC Electrical Characteristics,” on page 25. • Updated Table 5.1, “ADC0 Electrical Characteristics,” on page 56. • Various small text changes. • Updated Table 8.1, “Voltage Regulator Electrical Specifications,” on page 69. •... - Page 275 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D OTES Rev. 1.3...
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Page 276: Contact Information
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