Figure 15.4. Crossbar Priority Decoder In Example Configuration - Silicon Laboratories C8051F341 Product Manual

P0
SF Signals
(32-pin
Package)
SF Signals
(48-pin
Package)
PIN I/O
0 1 2 3 4 5
TX0
RX0
SCK
MISO
MOSI
NSS*
*NSS is only pinned out in 4-wire SPI mode
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1**
RX1**
0 0 0 0 0 0
P0SKIP[0:7]
Port pin assigned to peripheral by the Crossbar
SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are

Figure 15.4. Crossbar Priority Decoder in Example Configuration

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
P1
6 7 0 1 2 3 4 5 6
0 0 0 0 0 0 0 0 0
P1SKIP[0:7]
(No Pins Skipped)
Rev. 1.3
P2
7 0 1 2 3 4 5 6 7
**UART1 available only on C8051F340/1/4/5/8/A/B devices
0 0 0 0 0 0 0 0 0
P2SKIP[0:7]
Example:
P3
P3.1-P3.7 unavailable on
the 32-pin packages
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
P3SKIP[0:7]
XBR0 = 0x07
XBR1 = 0x43
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