Edge-Triggered Capture Mode; Figure 22.4. Pca Capture Mode Diagram - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

22.2.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
Port I/O Crossbar
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by
the hardware.
258
PCA0CPMn
P
E C C
W
C A A
M
O P P
1
M P N
6
n n n
n
x 0
0
1
CEXn

Figure 22.4. PCA Capture Mode Diagram

Rev. 1.3
PCA Interrupt
PCA0CN
P
M T E
W C C C C C C C
A O C
M F R C C C C C
T G C
n
F F F F F
n n F
4 3 2 1 0
n
0 0 0 x
Capture
0
1
PCA
Timebase
PCA0CPLn PCA0CPHn
PCA0L PCA0H