Bit Adc (Adc0, C8051F340/1/2/3/4/5/6/7/A/B Only); Figure 5.1. Adc0 Functional Block Diagram - Silicon Laboratories C8051F341 Product Manual

5.

10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)

The ADC0 subsystem for the C8051F34x devices consists of two analog multiplexers (referred to collec-
tively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window
detector are all configured under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages
at port pins, the Temperature Sensor output, or V
tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
Port I/O
Pins*
Positive
Input
VDD
(AIN+)
AMUX
Temp
Sensor
Port I/O
Pins*
Negative
Input
VREF
(AIN-)
AMUX
GND
* 21 Selections on 32-pin package
20 Selections on 48-pin package

Figure 5.1. ADC0 Functional Block Diagram

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
with respect to a port pin, VREF, or GND. The connec-
DD
AMX0P
AIN+
AIN-
AMX0N ADC0CF
Rev. 1.3
ADC0CN
VDD
000
Start
001
Conversion
010
011
100
101
10-Bit
SAR
ADC
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
AD0WINT
Window
Compare
32
Logic
41