Table 16.2. Usb0 Controller Registers; Usb Register Definition 16.4. Index: Usb0 Endpoint Index - Silicon Laboratories C8051F341 Product Manual

USB Register USB Register
Name Address
IN1INT 0x02
OUT1INT 0x04
CMINT 0x06
IN1IE 0x07
OUT1IE 0x09
CMIE 0x0B
FADDR 0x00
POWER 0x01
FRAMEL 0x0C
FRAMEH 0x0D
INDEX 0x0E
CLKREC 0x0F
FIFOn 0x20–0x23
E0CSR
0x11
EINCSRL
EINCSRH 0x12
EOUTCSRL 0x14
EOUTCSRH 0x15
E0CNT
0x16
EOUTCNTL
EOUTCNTH 0x17

USB Register Definition 16.4. INDEX: USB0 Endpoint Index

R R
- -
Bit7 Bit6
Bits7–4: Unused. Read = 0000b; Write = don't care.
Bits3–0: EPSEL: Endpoint Select
These bits select which endpoint is targeted when indexed USB0 registers are accessed.
INDEX
0x0
0x1
0x2
0x3
0x4–0xF
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

Table 16.2. USB0 Controller Registers

Interrupt Registers
Endpoint0 and Endpoints1-3 IN Interrupt Flags
Endpoints1-3 OUT Interrupt Flags
Common USB Interrupt Flags
Endpoint0 and Endpoints1-3 IN Interrupt Enables
Endpoints1-3 OUT Interrupt Enables
Common USB Interrupt Enables
Common Registers
Function Address
Power Management
Frame Number Low Byte
Frame Number High Byte
Endpoint Index Selection
Clock Recovery Control
Endpoints0-3 FIFOs
Indexed Registers
Endpoint0 Control / Status
Endpoint IN Control / Status Low Byte
Endpoint IN Control / Status High Byte
Endpoint OUT Control / Status Low Byte
Endpoint OUT Control / Status High Byte
Number of Received Bytes in Endpoint0 FIFO
Endpoint OUT Packet Count Low Byte
Endpoint OUT Packet Count High Byte
R R R/W
- -
Bit5 Bit4 Bit3
Target Endpoint
0
1
2
3
Reserved
Rev. 1.3
Description
R/W R/W
EPSEL
Bit2 Bit1
Page Number
173
173
174
175
175
176
169
171
172
172
165
166
168
179
182
183
185
186
180
186
186
R/W Reset Value
00000000
Bit0 USB Address:
0x0E
165