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Silicon Laboratories C8051F34C Manuals
Manuals and User Guides for Silicon Laboratories C8051F34C. We have
1
Silicon Laboratories C8051F34C manual available for free PDF download: Product Manual
Silicon Laboratories C8051F34C Product Manual (276 pages)
Full Speed USB Flash MCU Family
Brand:
Silicon Laboratories
| Category:
Storage
| Size: 1 MB
Table of Contents
Table of Contents
3
System Overview
17
Table 1.1. Product Selection Guide
18
1 System Overview
19
Figure 1.1. C8051F340/1/4/5 Block Diagram
19
Figure 1.2. C8051F342/3/6/7 Block Diagram
20
Figure 1.3. C8051F348/C Block Diagram
21
Figure 1.4. C8051F349/D Block Diagram
22
Figure 1.5. C8051F34A/B Block Diagram
23
Absolute Maximum Ratings
24
Table 2.1. Absolute Maximum Ratings
24
Global DC Electrical Characteristics
25
Table 3.1. Global DC Electrical Characteristics
25
Table 3.2. Index to Electrical Characteristics Tables
27
4 Pinout and Package Definitions
28
Pinout and Package Definitions
28
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
28
4 Pinout and Package Definitions
31
Figure 4.1. TQFP-48 Pinout Diagram (Top View)
31
Figure 4.2. TQFP-48 Package Diagram
32
Table 4.2. TQFP-48 Package Dimensions
32
Figure 4.3. TQFP-48 Recommended PCB Land Pattern
33
Table 4.3. TQFP-48 PCB Land Pattern Dimensions
33
Figure 4.4. LQFP-32 Pinout Diagram (Top View)
34
Figure 4.5. LQFP-32 Package Diagram
35
Table 4.4. LQFP-32 Package Dimensions
35
Figure 4.6. LQFP-32 Recommended PCB Land Pattern
36
Table 4.5. LQFP-32 PCB Land Pattern Dimensions
36
Figure 4.7. QFN-32 Pinout Diagram (Top View)
37
5 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
41
Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
41
Figure 5.1. ADC0 Functional Block Diagram
41
Analog Multiplexer
42
Temperature Sensor
43
Figure 5.2. Temperature Sensor Transfer Function
43
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
44
Modes of Operation
45
Starting a Conversion
45
Tracking Modes
46
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
46
Settling Time Requirements
47
Figure 5.5. ADC0 Equivalent Input Circuits
47
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
48
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
49
SFR Definition 5.3. ADC0CF: ADC0 Configuration
50
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
50
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
50
SFR Definition 5.6. ADC0CN: ADC0 Control
51
Programmable Window Detector
52
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
52
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
52
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
53
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
53
Window Detector in Single-Ended Mode
54
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
54
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
54
Window Detector in Differential Mode
55
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
55
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
55
5 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
56
Table 5.1. ADC0 Electrical Characteristics
56
6 Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
57
Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
57
Figure 6.1. Voltage Reference Functional Block Diagram
57
6 Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
58
Table 6.1. Voltage Reference Electrical Characteristics
58
SFR Definition 6.1. REF0CN: Reference Control
58
Comparators
59
7 Comparators
60
Figure 7.1. Comparator Functional Block Diagram
60
Figure 7.2. Comparator Hysteresis Plot
61
SFR Definition 7.1. CPT0CN: Comparator0 Control
62
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
63
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
64
SFR Definition 7.4. CPT1CN: Comparator1 Control
65
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
66
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
67
7 Comparators
68
Table 7.1. Comparator Electrical Characteristics
68
8 Voltage Regulator (REG0)
69
Voltage Regulator (REG0)
69
Regulator Mode Selection
69
VBUS Detection
69
Table 8.1. Voltage Regulator Electrical Specifications
69
8 Voltage Regulator (REG0)
70
Figure 8.1. REG0 Configuration: USB Bus-Powered
70
Figure 8.2. REG0 Configuration: USB Self-Powered
70
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
71
Figure 8.4. REG0 Configuration: no USB Connection
71
SFR Definition 8.1. REG0CN: Voltage Regulator Control
72
9 CIP-51 Microcontroller
73
Microcontroller
73
Figure 9.1. CIP-51 Block Diagram
73
Instruction Set
74
Instruction and CPU Timing
74
MOVX Instruction and Program Memory
75
Table 9.1. CIP-51 Instruction Set Summary
75
Memory Organization
79
Figure 9.2. On-Chip Memory Map for 64 Kb Devices
79
Figure 9.3. On-Chip Memory Map for 32 Kb Devices
80
Program Memory
80
Bit Addressable Locations
81
Data Memory
81
General Purpose Registers
81
Stack
81
Special Function Registers
82
Table 9.2. Special Function Register (SFR) Memory Map
82
Table 9.3. Special Function Registers
83
Register Descriptions
86
9 CIP-51 Microcontroller
75
SFR Definition 9.1. DPL: Data Pointer Low Byte
86
SFR Definition 9.2. DPH: Data Pointer High Byte
86
SFR Definition 9.3. SP: Stack Pointer
86
SFR Definition 9.4. PSW: Program Status Word
87
SFR Definition 9.5. ACC: Accumulator
87
Interrupt Handler
88
MCU Interrupt Sources and Vectors
88
External Interrupts
88
SFR Definition 9.6. B: B Register
88
Interrupt Priorities
89
Interrupt Latency
89
Interrupt Register Descriptions
90
Table 9.4. Interrupt Summary
90
SFR Definition 9.7. IE: Interrupt Enable
91
SFR Definition 9.8. IP: Interrupt Priority
92
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1
93
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1
94
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2
95
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2
95
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration
96
Power Management Modes
97
Idle Mode
97
Stop Mode
97
SFR Definition 9.14. PCON: Power Control
98
Prefetch Engine
99
11 Reset Sources
100
Reset Sources
100
Figure 11.1. Reset Sources
100
Power-On Reset
101
Figure 11.2. Power-On and VDD Monitor Reset Timing
101
Power-Fail Reset / VDD Monitor
102
External Reset
103
Missing Clock Detector Reset
103
Comparator0 Reset
103
PCA Watchdog Timer Reset
103
Flash Error Reset
103
Software Reset
104
USB Reset
104
SFR Definition 11.2. RSTSRC: Reset Source
105
11 Reset Sources
106
Table 11.1. Reset Electrical Characteristics
106
Flash Memory
107
Programming the Flash Memory
107
Flash Lock and Key Functions
107
Flash Erase Procedure
107
Flash Write Procedure
108
12 Flash Memory
109
Non-Volatile Data Storage
109
Security Options
109
Table 12.1. Flash Electrical Characteristics
109
12 Flash Memory
110
Figure 12.1. Flash Program Memory Map and Security Byte
110
SFR Definition 12.1. PSCTL: Program Store R/W Control
112
SFR Definition 12.2. FLKEY: Flash Lock and Key
112
SFR Definition 12.3. FLSCL: Flash Scale
113
External Data Memory Interface and On-Chip XRAM
114
Accessing XRAM
114
16-Bit MOVX Example
114
13 External Data Memory Interface and On-Chip XRAM
115
Accessing USB FIFO Space
115
Figure 13.1. USB FIFO Space and XRAM Memory Map
115
Configuring the External Memory Interface
116
Port Configuration
116
SFR Definition 13.1. EMI0CN: External Memory Interface Control
117
SFR Definition 13.2. EMI0CF: External Memory Configuration
118
Multiplexed and Non-Multiplexed Selection
119
Multiplexed Configuration
119
Figure 13.2. Multiplexed Configuration Example
119
Non-Multiplexed Configuration
120
Memory Mode Selection
120
Figure 13.3. Non-Multiplexed Configuration Example
120
Figure 13.4. EMIF Operating Modes
120
Internal XRAM Only
121
Split Mode Without Bank Select
121
External Only
122
Split Mode with Bank Select
122
Timing
122
SFR Definition 13.3. EMI0TC: External Memory Timing Control
123
Non-Multiplexed Mode
124
Figure 13.5. Non-Multiplexed 16-Bit MOVX Timing
124
Figure 13.6. Non-Multiplexed 8-Bit MOVX Without Bank Select Timing
125
Figure 13.7. Non-Multiplexed 8-Bit MOVX with Bank Select Timing
126
Multiplexed Mode
127
Figure 13.8. Multiplexed 16-Bit MOVX Timing
127
Figure 13.9. Multiplexed 8-Bit MOVX Without Bank Select Timing
128
Figure 13.10. Multiplexed 8-Bit MOVX with Bank Select Timing
129
13 External Data Memory Interface and On-Chip XRAM
130
Table 13.1. AC Parameters for External Memory Interface
130
14 Oscillators
131
Oscillators
131
Figure 14.1. Oscillator Diagram
131
Programmable Internal High-Frequency (H-F) Oscillator
132
Internal H-F Oscillator Suspend Mode
132
SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control
132
Programmable Internal Low-Frequency (L-F) Oscillator
133
Calibrating the Internal L-F Oscillator
133
SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration
133
SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control
134
External Oscillator Drive Circuit
135
Clocking Timers Directly through the External Oscillator
135
External Crystal Example
135
External RC Example
136
External Capacitor Example
136
SFR Definition 14.4. OSCXCN: External Oscillator Control
137
Clock Multiplier
138
SFR Definition 14.5. CLKMUL: Clock Multiplier Control
138
System and USB Clock Selection
139
System Clock Selection
139
USB Clock Selection
139
SFR Definition 14.6. CLKSEL: Clock Select
140
14 Oscillators
141
Table 14.1. Oscillator Electrical Characteristics
141
15 Port Input/Output
142
Port Input/Output
142
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
142
Figure 15.2. Port I/O Cell Block Diagram
143
Figure 15.3. Peripheral Availability on Port I/O Pins
144
Priority Crossbar Decoder
144
Figure 15.4. Crossbar Priority Decoder in Example Configuration
145
Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
146
Port I/O Initialization
147
SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0
148
SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1
149
SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2
149
General Purpose Port I/O
150
SFR Definition 15.4. P0: Port0 Latch
150
SFR Definition 15.5. P0MDIN: Port0 Input Mode
150
SFR Definition 15.6. P0MDOUT: Port0 Output Mode
151
SFR Definition 15.7. P0SKIP: Port0 Skip
151
SFR Definition 15.8. P1: Port1 Latch
152
SFR Definition 15.9. P1MDIN: Port1 Input Mode
152
SFR Definition 15.10. P1MDOUT: Port1 Output Mode
152
SFR Definition 15.11. P1SKIP: Port1 Skip
153
SFR Definition 15.12. P2: Port2 Latch
153
SFR Definition 15.13. P2MDIN: Port2 Input Mode
153
SFR Definition 15.14. P2MDOUT: Port2 Output Mode
154
SFR Definition 15.15. P2SKIP: Port2 Skip
154
SFR Definition 15.16. P3: Port3 Latch
155
SFR Definition 15.17. P3MDIN: Port3 Input Mode
155
SFR Definition 15.18. P3MDOUT: Port3 Output Mode
155
SFR Definition 15.19. P3SKIP: Port3 Skip
156
SFR Definition 15.20. P4: Port4 Latch
156
SFR Definition 15.21. P4MDIN: Port4 Input Mode
157
SFR Definition 15.22. P4MDOUT: Port4 Output Mode
157
15 Port Input/Output
158
Table 15.1. Port I/O DC Electrical Characteristics
158
16 Universal Serial Bus Controller (USB0)
159
Universal Serial Bus Controller (USB0)
159
Figure 16.1. USB0 Block Diagram
159
Endpoint Addressing
160
USB Transceiver
160
Table 16.1. Endpoint Addressing Scheme
160
16 Universal Serial Bus Controller (USB0)
160
SFR Definition 16.1. USB0XCN: USB0 Transceiver Control
161
USB Register Access
162
Figure 16.2. USB0 Register Access Scheme
162
SFR Definition 16.2. USB0ADR: USB0 Indirect Address
163
SFR Definition 16.3. USB0DAT: USB0 Data
164
Table 16.2. USB0 Controller Registers
165
USB Register Definition 16.4. INDEX: USB0 Endpoint Index
165
USB Clock Configuration
166
USB Register Definition 16.5. CLKREC: Clock Recovery Control
166
FIFO Management
167
FIFO Split Mode
167
Figure 16.3. USB FIFO Allocation
167
FIFO Double Buffering
168
FIFO Access
168
Table 16.3. FIFO Configurations
168
USB Register Definition 16.6. Fifon: USB0 Endpoint FIFO Access
168
Function Addressing
169
Function Configuration and Control
169
USB Register Definition 16.7. FADDR: USB0 Function Address
169
USB Register Definition 16.8. POWER: USB0 Power
171
Interrupts
172
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low
172
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High
172
USB Register Definition 16.11. IN1INT: USB0 in Endpoint Interrupt
173
USB Register Definition 16.12. OUT1INT: USB0 out Endpoint Interrupt
173
USB Register Definition 16.13. CMINT: USB0 Common Interrupt
174
USB Register Definition 16.14. IN1IE: USB0 in Endpoint Interrupt Enable
175
USB Register Definition 16.15. OUT1IE: USB0 out Endpoint Interrupt Enable
175
The Serial Interface Engine
176
Endpoint0
176
USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable
176
Endpoint0 SETUP Transactions
177
Endpoint0 in Transactions
177
Endpoint0 out Transactions
178
USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control
179
Configuring Endpoints1-3
180
Controlling Endpoints1-3 in
180
Endpoints1-3 in Interrupt or Bulk Mode
180
USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count
180
Endpoints1-3 in Isochronous Mode
181
USB Register Definition 16.19. EINCSRL: USB0 in Endpoint Control Low Byte
182
Controlling Endpoints1-3 out
183
Endpoints1-3 out Interrupt or Bulk Mode
183
Endpoints1-3 out Isochronous Mode
184
Endpoint Control Low Byte
185
Endpoint Control High Byte
186
USB Register Definition 16.23. EOUTCNTL: USB0 out Endpoint Count Low
186
USB Register Definition 16.24. EOUTCNTH: USB0 out Endpoint Count High
186
Table 16.4. USB Transceiver Electrical Characteristics
187
17 Smbus
188
Smbus
188
Figure 17.1. Smbus Block Diagram
188
Supporting Documents
189
Smbus Configuration
189
Smbus Operation
189
Figure 17.2. Typical Smbus Configuration
189
Arbitration
190
Figure 17.3. Smbus Transaction
190
Clock Low Extension
191
SCL High (Smbus Free) Timeout
191
SCL Low Timeout
191
Using the Smbus
191
Smbus Configuration Register
192
Table 17.1. Smbus Clock Source Selection
192
Figure 17.4. Typical Smbus SCL Generation
193
Table 17.2. Minimum SDA Setup and Hold Times
193
17 Smbus
192
SFR Definition 17.1. SMB0CF: Smbus Clock/Configuration
194
SMB0CN Control Register
195
SFR Definition 17.2. SMB0CN: Smbus Control
196
Table 17.3. Sources for Hardware Changes to SMB0CN
197
Data Register
198
Smbus Transfer Modes
198
Master Transmitter Mode
198
SFR Definition 17.3. SMB0DAT: Smbus Data
198
Figure 17.5. Typical Master Transmitter Sequence
199
Figure 17.6. Typical Master Receiver Sequence
200
Master Receiver Mode
200
Figure 17.7. Typical Slave Receiver Sequence
201
Slave Receiver Mode
201
Figure 17.8. Typical Slave Transmitter Sequence
202
Slave Transmitter Mode
202
Smbus Status Decoding
202
Table 17.4. Smbus Status Decoding
203
18 Uart0
205
Uart0
205
Figure 18.1. UART0 Block Diagram
205
Enhanced Baud Rate Generation
206
Operational Modes
206
Figure 18.2. UART0 Baud Rate Logic
206
8-Bit UART
207
Figure 18.3. UART Interconnect Diagram
207
Figure 18.4. 8-Bit UART Timing Diagram
207
9-Bit UART
208
Multiprocessor Communications
208
Figure 18.5. 9-Bit UART Timing Diagram
208
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram
209
SFR Definition 18.1. SCON0: Serial Port 0 Control
210
SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer
211
18 Uart0
212
Table 18.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator
212
UART1 (C8051F340/1/4/5/8/A/B/C Only)
213
Figure 19.1. UART1 Block Diagram
213
Baud Rate Generator
214
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates
214
Data Format
215
Figure 19.2. UART1 Timing Without Parity or Extra Bit
215
Figure 19.3. UART1 Timing with Parity
215
Figure 19.4. UART1 Timing with Extra Bit
215
Configuration and Operation
216
Data Transmission
216
Data Reception
216
Figure 19.5. Typical UART Interconnect Diagram
216
Multiprocessor Communications
217
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram
218
19 UART1 (C8051F340/1/4/5/8/A/B/C Only)
214
SFR Definition 19.1. SCON1: UART1 Control
218
SFR Definition 19.2. SMOD1: UART1 Mode
219
SFR Definition 19.3. SBUF1: UART1 Data Buffer
220
SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control
220
SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte
221
SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte
221
20 Enhanced Serial Peripheral Interface (SPI0)
222
Enhanced Serial Peripheral Interface (SPI0)
222
Figure 20.1. SPI Block Diagram
222
Signal Descriptions
223
Master Out, Slave in (MOSI)
223
Master In, Slave out (MISO)
223
Serial Clock (SCK)
223
Slave Select (NSS)
223
SPI0 Master Mode Operation
224
Figure 20.2. Multiple-Master Mode Connection Diagram
225
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram
225
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram
225
SPI0 Slave Mode Operation
226
SPI0 Interrupt Sources
226
Serial Clock Timing
227
Figure 20.5. Master Mode Data/Clock Timing
227
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)
228
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)
228
SPI Special Function Registers
229
SFR Definition 20.1. SPI0CFG: SPI0 Configuration
229
SFR Definition 20.2. SPI0CN: SPI0 Control
230
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate
231
SFR Definition 20.4. SPI0DAT: SPI0 Data
231
Figure 20.8. SPI Master Timing (CKPHA = 0)
232
Figure 20.9. SPI Master Timing (CKPHA = 1)
232
Figure 20.10. SPI Slave Timing (CKPHA = 0)
233
Figure 20.11. SPI Slave Timing (CKPHA = 1)
233
20 Enhanced Serial Peripheral Interface (SPI0)
234
Table 20.1. SPI Slave Timing Parameters
234
Timers
235
Timer 0 and Timer 1
235
Mode 0: 13-Bit Counter/Timer
235
Mode 1: 16-Bit Counter/Timer
236
Figure 21.1. T0 Mode 0 Block Diagram
236
Mode 2: 8-Bit Counter/Timer with Auto-Reload
237
Figure 21.2. T0 Mode 2 Block Diagram
237
Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)
238
Figure 21.3. T0 Mode 3 Block Diagram
238
21 Timers
236
SFR Definition 21.1. TCON: Timer Control
239
SFR Definition 21.2. TMOD: Timer Mode
240
SFR Definition 21.3. CKCON: Clock Control
241
SFR Definition 21.4. TL0: Timer 0 Low Byte
242
SFR Definition 21.5. TL1: Timer 1 Low Byte
242
SFR Definition 21.6. TH0: Timer 0 High Byte
242
SFR Definition 21.7. TH1: Timer 1 High Byte
242
Timer 2
243
16-Bit Timer with Auto-Reload
243
Figure 21.4. Timer 2 16-Bit Mode Block Diagram
243
8-Bit Timers with Auto-Reload
244
Figure 21.5. Timer 2 8-Bit Mode Block Diagram
244
Timer 2 Capture Modes: USB Start-Of-Frame or LFO Falling Edge
245
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = '0')
245
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = '1')
246
SFR Definition 21.8. TMR2CN: Timer 2 Control
247
SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte
248
SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte
248
SFR Definition 21.11. TMR2L: Timer 2 Low Byte
248
SFR Definition 21.12. TMR2H Timer 2 High Byte
248
Timer 3
249
16-Bit Timer with Auto-Reload
249
Figure 21.8. Timer 3 16-Bit Mode Block Diagram
249
8-Bit Timers with Auto-Reload
250
Figure 21.9. Timer 3 8-Bit Mode Block Diagram
250
USB Start-Of-Frame Capture
251
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = '0')
251
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = '1')
252
SFR Definition 21.13. TMR3CN: Timer 3 Control
253
SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte
254
SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte
254
SFR Definition 21.16. TMR3L: Timer 3 Low Byte
254
SFR Definition 21.17. TMR3H Timer 3 High Byte
254
22 Programmable Counter Array (PCA0)
255
Programmable Counter Array (PCA0)
255
Figure 22.1. PCA Block Diagram
255
PCA Counter/Timer
256
Figure 22.2. PCA Counter/Timer Block Diagram
256
Table 22.1. PCA Timebase Input Options
256
Capture/Compare Modules
257
Figure 22.3. PCA Interrupt Block Diagram
257
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
257
Edge-Triggered Capture Mode
258
Figure 22.4. PCA Capture Mode Diagram
258
Figure 22.5. PCA Software Timer Mode Diagram
259
Software Timer (Compare) Mode
259
Figure 22.6. PCA High Speed Output Mode Diagram
260
High Speed Output Mode
260
Figure 22.7. PCA Frequency Output Mode
261
Frequency Output Mode
261
8-Bit Pulse Width Modulator Mode
262
Figure 22.8. PCA 8-Bit PWM Mode Diagram
262
16-Bit Pulse Width Modulator Mode
263
Figure 22.9. PCA 16-Bit PWM Mode
263
Watchdog Timer Mode
264
Watchdog Timer Operation
264
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled
264
Watchdog Timer Usage
265
Table 22.3. Watchdog Timer Timeout Intervals1
265
Register Descriptions for PCA
266
22 Programmable Counter Array (PCA0)
256
SFR Definition 22.1. PCA0CN: PCA Control
266
SFR Definition 22.2. PCA0MD: PCA Mode
267
SFR Definition 22.3. Pca0Cpmn: PCA Capture/Compare Mode
268
SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte
269
SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte
269
SFR Definition 22.6. Pca0Cpln: PCA Capture Module Low Byte
269
SFR Definition 22.7. Pca0Cphn: PCA Capture Module High Byte
270
C2 Interface
271
C2 Interface Registers
271
C2 Register Definition 23.1. C2ADD: C2 Address
271
C2 Register Definition 23.2. DEVICEID: C2 Device ID
271
C2 Register Definition 23.3. REVID: C2 Revision ID
272
C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control
272
C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data
272
23 C2 Interface
273
C2 Pin Sharing
273
Figure 23.1. Typical C2 Pin Sharing
273
Document Change List
274
Contact Information
276
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Silicon Laboratories C8051F340
Silicon Laboratories C8051F342
Silicon Laboratories C8051F347
Silicon Laboratories C8051F343
Silicon Laboratories C8051F344
Silicon Laboratories C8051F348
Silicon Laboratories C8051F349
Silicon Laboratories C8051F34A
Silicon Laboratories C8051F34B
Silicon Laboratories Categories
Motherboard
Microcontrollers
Computer Hardware
Control Unit
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