Figure 1.4. C8051F349/D Block Diagram - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
C2D
C2CK/RST
Reset
Power-On
Reset
Supply
Monitor
VDD
Power
Net
Voltage
VREG
Regulator
GND
XTAL1
XTAL2
D+
D-
VBUS
22
Debug / Programming
Hardware
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
SFR
Bus
System Clock Setup
External
Oscillator
Clock
Multiplier
Internal
Oscillator
Clock Low Freq.
Recovery Oscillator
USB Peripheral
Controller
Full / Low
Speed
Transceiver
1 kB RAM

Figure 1.4. C8051F349/D Block Diagram

Rev. 1.3
Port I/O Configuration
Digital Peripherals
UART0
Drivers
Timers 0, 1,
2, 3 Priority
Crossbar
Drivers
Decoder
PCA/WDT
SMBus
SPI
Drivers
Crossbar Control
Drivers
Analog Peripherals
CP0
+
-
CP1
+
-
2 Comparators
P0.0
P0.1
P0.2/XTAL1
Port 0
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
Port 1
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
Port 2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Port 3