Silicon Laboratories C8051F341 Product Manual page 85

Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address
SBUF0 0x99
SCON0 0x98
SMB0CF 0xC1
SMB0CN 0xC0
SMB0DAT 0xC2
SMOD1 0xE5
SP 0x81
SPI0CFG 0xA1
SPI0CKR 0xA2
SPI0CN 0xF8
SPI0DAT 0xA3
TCON 0x88
TH0 0x8C
TH1 0x8D
TL0 0x8A
TL1 0x8B
TMOD 0x89
TMR2CN 0xC8
TMR2H 0xCD
TMR2L 0xCC
TMR2RLH 0xCB
TMR2RLL 0xCA
TMR3CN 0x91
TMR3H 0x95
TMR3L 0x94
TMR3RLH 0x93
TMR3RLL 0x92
VDM0CN 0xFF
USB0ADR 0x96
USB0DAT 0x97
USB0XCN 0xD7
XBR0 0xE1
XBR1 0xE2
XBR2 0xE3
All Other Addresses
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Description
UART0 Data Buffer
UART0 Control
SMBus Configuration
SMBus Control
SMBus Data
UART1 Mode
Stack Pointer
SPI Configuration
SPI Clock Rate Control
SPI Control
SPI Data
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3Control
Timer/Counter 3 High
Timer/Counter 3Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
V Monitor Control
DD
USB0 Indirect Address Register
USB0 Data Register
USB0 Transceiver Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
Reserved
Rev. 1.3
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