Silicon Laboratories C8051F341 Product Manual page 38

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Dimension
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
variation VHHD except for custom features D2, E2, and L which are
toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
38
Figure 4.8. QFN-32 Package Drawing
Table 4.6. QFN-32 Package Dimensions
Min
A 0.80
A1 0.00
b 0.18
D
D2 3.20
e
E
E2 3.20
L 0.30
Rev. 1.3
Nom Max
0.9 1.00
0.02 0.05
0.25 0.30
5.00 BSC
3.30 3.40
0.50 BSC
5.00 BSC
3.30 3.40
0.40 0.50