Non-Multiplexed Configuration; Memory Mode Selection; Figure 13.3. Non-Multiplexed Configuration Example; Figure 13.4. Emif Operating Modes - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

13.5.2. Non-multiplexed Configuration

In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 13.3. See
page 124 for more information about Non-multiplexed operation.
A[15:0]
E
M
I
D[7:0]
F
WR
RD

Figure 13.3. Non-multiplexed Configuration Example

13.6. Memory Mode Selection

The external data memory space can be configured in one of four modes, shown in Figure 13.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 13.2). These modes are summarized below.
More information about the different modes can be found in
EMI0CF[3:2] = 00
0xFFFF
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
120
ADDRESS BUS
(Optional)
DATA BUS
EMI0CF[3:2] = 01
0xFFFF
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0x0000

Figure 13.4. EMIF Operating Modes

Rev. 1.3
Section "13.7.1. Non-multiplexed Mode" on
V
DD
8
Section "13.7. Timing" on page
EMI0CF[3:2] = 10
0xFFFF
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
0x0000
A[15:0]
64K X 8
SRAM
I/O[7:0]
CE
WE
OE
122.
EMI0CF[3:2] = 11
0xFFFF
Off-Chip
Memory
0x0000