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Silicon Laboratories C8051F302 Manuals
Manuals and User Guides for Silicon Laboratories C8051F302. We have
1
Silicon Laboratories C8051F302 manual available for free PDF download: Manual
Silicon Laboratories C8051F302 Manual (178 pages)
Mixed Signal ISP Flash MCU Family
Brand:
Silicon Laboratories
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
3
1 System Overview
13
Table 1.1. Product Selection Guide
14
Figure 1.1. C8051F300/2 Block Diagram
15
Figure 1.2. C8051F301/3/4/5 Block Diagram
15
Smbus
15
Microcontroller Core
16
Fully 8051 Compatible
16
Improved Throughput
16
Figure 1.3. Comparison of Peak MCU Execution Speeds
16
Microcontroller
16
Additional Features
17
Figure 1.4. On-Chip Clock and Reset
17
Figure 1.5. On-Chip Memory Map (C8051F300/1/2/3 Shown)
18
On-Chip Memory
18
Figure 1.6. Development/In-System Debug Diagram
19
On-Chip Debug Circuitry
19
Programmable Digital I/O and Crossbar
19
Figure 1.7. Digital Crossbar Diagram
20
Serial Ports
20
Figure 1.8. PCA Block Diagram
21
Figure 1.9. PCA Block Diagram
21
Programmable Counter Array
21
8-Bit Analog to Digital Converter (C8051F300/2 Only)
22
Figure 1.10. 8-Bit ADC Block Diagram
22
Comparator
23
Figure 1.11. Comparator Block Diagram
23
2 Absolute Maximum Ratings
24
Table 2.1. Absolute Maximum Ratings
24
3 Global Electrical Characteristics
25
Table 3.1. Global Electrical Characteristics
25
4 Pinout and Package Definitions
27
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
27
Figure 4.1. QFN-11 Pinout Diagram (Top View)
28
Figure 4.2. QFN-11 Package Drawing
29
Table 4.2. QFN-11 Package Dimensions
29
Figure 4.3. Typical QFN-11 Solder Paste Mask
30
Figure 4.4. Typical QFN-11 Landing Diagram
31
Table 4.3. QFN-11 Landing Diagram Dimensions
31
Figure 4.5. SOIC-14 Pinout Diagram (Top View)
32
Figure 4.6. SOIC-14 Package Drawing
33
Table 4.4. SOIC-14 Package Dimensions
33
Figure 4.7. SOIC-14 PCB Land Pattern
34
Table 4.5. SOIC-14 PCB Land Pattern Dimensions
34
5 ADC0 (8-Bit ADC, C8051F300/2)
35
Figure 5.1. ADC0 Functional Block Diagram
35
Analog Multiplexer and
36
Port Input/Output
36
Temperature Sensor
36
Figure 5.2. Typical Temperature Sensor Transfer Function
37
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
38
Modes of Operation
39
Starting a Conversion
39
Tracking Modes
40
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing
40
Settling Time Requirements
41
Figure 5.5. ADC0 Equivalent Input Circuits
41
Programmable Window Detector
45
Window Detector in Single-Ended Mode
45
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode
45
Window Detector in Differential Mode
46
Figure 5.7. ADC Window Compare Examples, Differential Mode
46
Table 5.1. ADC0 Electrical Characteristics
47
6 Voltage Reference (C8051F300/2)
49
Figure 6.1. Voltage Reference Functional Block Diagram
49
Table 6.1. External Voltage Reference Circuit Electrical Characteristics
50
7 Comparator0
51
Figure 7.1. Comparator0 Functional Block Diagram
51
Figure 7.2. Comparator Hysteresis Plot
52
Table 7.1. Comparator0 Electrical Characteristics
55
8 Microcontroller
57
Figure 8.1. CIP-51 Block Diagram
57
Instruction Set
58
Instruction and CPU Timing
58
MOVX Instruction and Program Memory
59
Table 8.1. CIP-51 Instruction Set Summary
59
Memory Organization
63
Program Memory
63
Figure 8.2. Program Memory Maps
63
Data Memory
64
General Purpose Registers
64
Figure 8.3. Data Memory Map
64
Bit Addressable Locations
65
Stack
65
Special Function Registers
65
Table 8.2. Special Function Register (SFR) Memory Map
66
Table 8.3. Special Function Registers
66
Register Descriptions
68
Interrupt Handler
72
MCU Interrupt Sources and Vectors
72
External Interrupts
73
Interrupt Priorities
73
Interrupt Latency
73
Table 8.4. Interrupt Summary
74
Interrupt Register Descriptions
75
Power Management Modes
80
Idle Mode
80
Stop Mode
81
9 Reset Sources
83
Figure 9.1. Reset Sources
83
Figure 9.2. Power-On and VDD Monitor Reset Timing
84
Power-Fail Reset/VDD Monitor
84
Power-On Reset
84
Comparator0 Reset
85
External Reset
85
Missing Clock Detector Reset
85
PCA Watchdog Timer Reset
85
Flash Error Reset
86
Software Reset
86
Table 9.1. User Code Space Address Limits
86
Table 9.2. Reset Electrical Characteristics
86
10 Flash Memory
89
Programming the Flash Memory
89
Flash Lock and Key Functions
89
Flash Erase Procedure
89
Flash Write Procedure
90
Non-Volatile Data Storage
90
Security Options
90
Table 10.1. Flash Electrical Characteristics
90
Figure 10.1. Flash Program Memory Map
91
Table 10.2. Security Byte Decoding
91
Flash Write and Erase Guidelines
94
VDD Maintenance and the VDD Monitor
94
PSWE Maintenance
94
System Clock
95
11 Oscillators
97
Programmable Internal Oscillator
97
Figure 11.1. Oscillator Diagram
97
External Oscillator Drive Circuit
99
System Clock Selection
99
Table 11.1. Internal Oscillator Electrical Characteristics
99
External Crystal Example
101
Figure 11.2. 32.768 Khz External Crystal Example
101
External RC Example
102
External Capacitor Example
102
12 Port Input/Output
103
Figure 12.1. Port I/O Functional Block Diagram
103
Figure 12.2. Port I/O Cell Block Diagram
103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0X00
104
Priority Crossbar Decoder
104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0X44
105
Port I/O Initialization
106
General Purpose Port I/O
108
Table 12.1. Port I/O DC Electrical Characteristics
110
13 Smbus
111
Figure 13.1. Smbus Block Diagram
111
Smbus Configuration
112
Smbus Operation
112
Figure 13.2. Typical Smbus Configuration
112
Arbitration
113
Figure 13.3. Smbus Transaction
113
Clock Low Extension
114
SCL High (Smbus Free) Timeout
114
SCL Low Timeout
114
Supporting Documents
112
Using the Smbus
115
Smbus Configuration Register
116
Table 13.1. Smbus Clock Source Selection
116
Figure 13.4. Typical Smbus SCL Generation
117
Table 13.2. Minimum SDA Setup and Hold Times
117
SMB0CN Control Register
119
Table 13.3. Sources for Hardware Changes to SMB0CN
121
Data Register
122
Smbus Transfer Modes
123
Master Transmitter Mode
123
Figure 13.5. Typical Master Transmitter Sequence
123
Master Receiver Mode
124
Figure 13.6. Typical Master Receiver Sequence
124
Slave Receiver Mode
125
Figure 13.7. Typical Slave Receiver Sequence
125
Slave Transmitter Mode
126
Figure 13.8. Typical Slave Transmitter Sequence
126
Smbus Status Decoding
127
Table 13.4. Smbus Status Decoding
127
14 Uart0
131
Figure 14.1. UART0 Block Diagram
131
Enhanced Baud Rate Generation
132
Figure 14.2. UART0 Baud Rate Logic
132
Uart0
132
Operational Modes
133
8-Bit UART
133
Figure 14.3. UART Interconnect Diagram
133
Figure 14.4. 8-Bit UART Timing Diagram
133
9-Bit UART
134
Figure 14.5. 9-Bit UART Timing Diagram
134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram
135
Multiprocessor Communications
135
Table 14.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 Mhz Oscillator
138
Table 14.2. Timer Settings for Standard Baud Rates Using an External 25 Mhz Oscillator
138
Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 Mhz Oscillator
139
Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 Mhz Oscillator
140
Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 Mhz Oscillator
141
Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ Oscillator
142
15 Timers
143
Timer 0 and Timer 1
143
Mode 0: 13-Bit Counter/Timer
143
Figure 15.1. T0 Mode 0 Block Diagram
144
Mode 1: 16-Bit Counter/Timer
145
Mode 2: 8-Bit Counter/Timer with Auto-Reload
145
Figure 15.2. T0 Mode 2 Block Diagram
145
Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)
146
Figure 15.3. T0 Mode 3 Block Diagram
146
Timer 2
151
16-Bit Timer with Auto-Reload
151
Figure 15.4. Timer 2 16-Bit Mode Block Diagram
151
8-Bit Timers with Auto-Reload
152
Figure 15.5. Timer 2 8-Bit Mode Block Diagram
152
16 Programmable Counter Array
155
Figure 16.1. PCA Block Diagram
155
Figure 16.2. PCA Counter/Timer Block Diagram
156
PCA Counter/Timer
156
Table 16.1. PCA Timebase Input Options
156
Capture/Compare Modules
157
Figure 16.3. PCA Interrupt Block Diagram
157
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
157
Edge-Triggered Capture Mode
158
Figure 16.4. PCA Capture Mode Diagram
158
Figure 16.5. PCA Software Timer Mode Diagram
159
Software Timer (Compare) Mode
159
Figure 16.6. PCA High Speed Output Mode Diagram
160
High Speed Output Mode
160
Figure 16.7. PCA Frequency Output Mode
161
Frequency Output Mode
161
8-Bit Pulse Width Modulator Mode
162
Figure 16.8. PCA 8-Bit PWM Mode Diagram
162
16-Bit Pulse Width Modulator Mode
163
Figure 16.9. PCA 16-Bit PWM Mode
163
Watchdog Timer Mode
164
Watchdog Timer Operation
164
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled
164
Watchdog Timer Usage
165
Table 16.3. Watchdog Timer Timeout Intervals
166
Register Descriptions for PCA
167
17 C2 Interface
173
C2 Interface Registers
173
C2 Pin Sharing
175
Figure 17.1. Typical C2 Pin Sharing
175
Document Change List
176
Oscillators
176
Contact Information
178
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