Usb Register Definition 16.6. Fifon: Usb0 Endpoint Fifo Access; Fifo Double Buffering; Fifo Access; Table 16.3. Fifo Configurations - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

16.5.2. FIFO Double Buffering

FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 16.3 for a list of maximum packet sizes for each FIFO configuration.
Endpoint Split Mode
Number Enabled?
0 N/A
N
1
Y
N
2
Y
N
3
Y

16.5.1. FIFO Access

Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.

USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access

R/W R/W
Bit7 Bit6
USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs:
IN/OUT Endpoint FIFO
0
1
2
3
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.
168

Table 16.3. FIFO Configurations

Maximum IN Packet Size (Dou-
ble Buffer Disabled / Enabled)
64 / 32
128 / 64
256 / 128
R/W R/W R/W
FIFODATA
Bit5 Bit4 Bit3
USB Address
0x20
0x21
0x22
0x23
Rev. 1.3
Maximum OUT Packet Size
(Double Buffer Disabled /
Enabled)
64
128 / 64
64 / 32
256 / 128
128 / 64
512 / 256
256 / 128
R/W R/W R/W
Bit2 Bit1 Bit0
Reset Value
00000000
USB Address:
0x20 - 0x23