Figure 20.8. Spi Master Timing (Ckpha = 0); Figure 20.9. Spi Master Timing (Ckpha = 1) - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SCK*
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 20.8. SPI Master Timing (CKPHA = 0)

SCK*
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 20.9. SPI Master Timing (CKPHA = 1)

232
T T
MCKH MCKL
T
MIS
T T
MCKH MCKL
T
MIS
Rev. 1.3
T
MIH
T
MIH