Reset Sources; Figure 11.1. Reset Sources - Silicon Laboratories C8051F341 Product Manual

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

11. Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section "14. Oscillators" on page 131
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section "22.3. Watchdog Timer Mode" on page 264
Program execution begins at location 0x0000.
Px.x
Px.x
Internal LF
Oscillator
Internal HF
Oscillator
Clock
Multiplier
External
XTAL1
Oscillator
XTAL2 Drive
100
Monitor and Power-On Resets, the RST pin is driven low until the device
DD
VDD
Supply
Monitor
+
-
Comparator 0
+
-
C0RSEF
Missing
Clock
Detector
(one-
PCA
shot)
WDT
EN
EN
System
Clock
CIP-51
Microcontroller System Reset
Core
Clock Select
Extended Interrupt
Handler

Figure 11.1. Reset Sources

Rev. 1.3
for information on selecting and configuring
details the use of the Watchdog Timer).
Enable
Power On
Reset
'0'
(wired-OR)
Software Reset (SWRSF)
Errant
FLASH
Operation
USB
Controller
RST
Reset
Funnel
VBUS
Transition