10/100 Intel Ethernet Phy (27) - Xilinx SP305 Spartan-3 User Manual

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Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY (Continued)

10/100 Intel Ethernet PHY (27)

The SP-305 Development Platform contains an Intel ® LXT971A 3.3V Dual-Speed Fast
Ethernet PHY Transceiver at 10/100 Mbps. A 25-MHz crystal supplies the clock signal to
the PHY. The PHY is configured to default at power-on or reset.
Table 2-17: 10/100 Intel Ethernet Clock Signals to PHY
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
Label
ENET_RD_N
ENET_WR_N
ENET_DATACS_N
ENET_CYCLE_N
ENET_RD_WR
ENET_VLBUS_N
XTAL1
XTAL2
ENET_X25OUT
ENET_TPOP
ENET_TPON
ENET_TPIP
ENET_TPIN
ENET_LNK_N
ENET_LBK
ENET_CNTRL_N
ENET_RBIAS
ENET_LEDA_N
ENET_LEDS_N
Label
PHY_TXD0
PHY_TXD1
PHY_TXD2
PHY_TXD3
PHY_TX_EN
PHY_TX_ER
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FPGA Pin
AA6
AB14
Pulled up to 3.3v
AC6
AD4
A12
N/A
N/A
AC7
N/A
N/A
N/A
N/A
N/C
N/C
N/A
Pulled down to GND
N/A
N/A
FPGA Pin
N1
N2
N3
N5
N8
N7
Detailed Description
Description
VLBUS
25MHz Crystal inputs
25MHz Crystal inputs
25 MHz Clock Output
RJ45 connector U1
RJ45 connector U1
RJ45 connector U1
RJ45 connector U1
RJ45 connector U1
RJ45 connector U1
RJ45 connector U1
Description
19