Mitsubishi Electric RD77GF8 User Manual page 29

■Data integrity assurance at the time of access to buffer memory
The integrity of 32-bit data can be assured by satisfying the following conditions.
• Access using the DMOV instruction
• The start address of the buffer memory is multiples of 2.
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For data assurance of more than 32 bits, use station-based block data assurance or interlock programs.
Station-based block data assurance
Integrity of the cyclic data is assured for each station by handshake between the CPU module and Simple Motion module for
a link refresh.
Precautions
• When the software version of the Simple Motion module is "Ver.01":
The set parameter is ignored in the Simple Motion module and operate as "Disable". Assure data using interlock programs
as required.
• When the software version of the Simple Motion module is "Ver.02" or later:
To enable data assurance in an asynchronous station, read/write data by direct access in the inter-module synchronous
interrupt program (I44) without using a link refresh. There are restrictions on the operation by the inter-module
synchronization setting, operation mode, and network synchronous communication.
<Inter-module synchronization valid>
Operation mode Network communication setting
Synchronous
High-speed Enable
Normal Enable
<Inter-module synchronization invalid>
Operation mode Network communication setting
Synchronous
High-speed Disable
Normal Disable
■Setting
Set station-based block data assurance under "Supplementary Cyclic Settings" in "Application Settings" of the master station.
(Page 74 Application Settings)
Once this setting is enabled on the master station, integrity of the data for all stations is assured for each station.
Simple Motion module
Buffer memory
2 words
(32 bits)
2 words
(32 bits)
DMOV instruction
2 words
(32 bits)
2 words
(32 bits)
0H
1H
2H
3H
4H
5H
6H
7H
Asynchronous
Disable
Enable
Asynchronous
Disable
Enable
1.3 Cyclic Transmission
1
1 FUNCTIONS
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