Table 2–53. SRAM Interface I/O (Part 1 of 3)
Board
Reference
U23 pin A1
Byte enables bit 0
U23 pin B2
Byte enables bit 1
U24 pin A1
Byte enables bit 2
U24 pin B2
Byte enables bit 3
U23, U24 pin J2
Clock (drives two memories)
U23, U24 pin B5
Chip select
U23, U24 pin A2
Output enable
U23, U24 pin A6
Power save /MRS set pin
U23 pin J1
Data wait bit 0
U24 pin J1
Data wait bit 1
U23, U24 pin G5
Write enable
U23, U24 pin J3
Address valid
U23, U24 pin A3
Address bit 1 (DWORD aligned)
U23, U24 pin A4
Address bit 2 (DWORD aligned)
U23, U24 pin A5
Address bit 3 (DWORD aligned)
U23, U24 pin B3
Address bit 4 (DWORD aligned)
U23, U24 pin B4
Address bit 5 (DWORD aligned)
U23, U24 pin C3
Address bit 6 (DWORD aligned)
Altera Corporation
March 2008
SRAM
The board features 8 MB of SRAM memory with a 32-bit data bus. The
devices use 1.8 V CMOS signaling and are optimized for low cost and
power.
The 32-bit interface is comprised of two x16 devices. The Samsung part
features a maximum frequency of 104 MHz (104 Mb/s). The theoretical
bandwidth of the entire interface is 416 MB/s.
The SRAM devices are part of a shared bus with connectivity to the
MAX II CPLD as well as the flash memory, which is called the FSM bus.
All three devices use 1.8 V CMOS signaling. Altera recommends to using
the 50 ohm OCT setting on the FPGA and the one-half drive setting on the
SRAM.
Table 2–53
lists the SRAM interface signal name, description, and I/O
standard. Signal names and type are relative to the Cyclone III device,
i.e., I/O setting and direction.
Description
Reference Manual
I/O
Schematic Signal
Standard
Name
1.8 V
SRAM_BEN0
1.8 V
SRAM_BEN1
1.8 V
SRAM_BEN2
1.8 V
SRAM_BEN3
1.8 V
SRAM_CLK
1.8 V
SRAM_CSN
1.8 V
SRAM_OEN
1.8 V
SRAM_PSN
1.8 V
SRAM_WAIT0
1.8 V
SRAM_WAIT1
1.8 V
SRAM_WEN
1.8 V
SRAM_ADVN
1.8 V
FSA1
1.8 V
FSA2
1.8 V
FSA3
1.8 V
FSA4
1.8 V
FSA5
1.8 V
FSA6
Cyclone III Development Board
Board Components
Cyclone III
Device Pin
Number
AF20
AH26
AE22
AB21
AD22
AB19
AD25
B4
AG15
AH25
AE25
AA19
AH10
AA13
AC10
Y15
AF22
AF26
2–67
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