Altera Cyclone III Reference Manual page 60

Communication Ports & Interface Cards
Table 2–44. Ethernet PHY Interface I/O (Part 2 of 2)
Board
Reference
U5 pin 93 RGMII interface receive data bus
bit 2
U5 pin 91 RGMII interface receive data bus
bit 3
U5 pin 94 RGMII interface receive control
U5 pin 11 RGMII interface transmit data
bus bit 0
U5 pin 12 RGMII interface transmit data
bus bit 1
U5 pin 14 RGMII interface transmit data
bus bit 2
U5 pin 16 RGMII interface transmit data
bus bit 3
U5 pin 9 RGMII interface transmit control 2.5 V
Table 2–45. RGMII Signal Definitions (Part 1 of 2)
Schematic Marvell Device
Signal Name
ENET_GTX_CLK GTX_CLK
ENET_TX_EN TX_EN
ENET_TXD[3:0] TXD[3:0]
ENET_RX_CLK RX_CLK
2–50
Cyclone III Development Board
Description
Table 2–45 is an excerpt from the Marvell data sheet with a summary of
the RGMII interface signals and their functions.
RGMII Spec
Pin Name Pin Name
TXC
TX_CTL
TD[3:0]
RXC
Reference Manual
I/O Schematic
Standard Signal Name
2.5 V
ENET_RX_D2
2.5 V
ENET_RX_D3
2.5 V
ENET_RX_DV
2.5 V
ENET_TX_D0
2.5 V
ENET_TX_D1
2.5 V
ENET_TX_D2
2.5 V
ENET_TX_D3
ENET_TX_EN
125 MHz, 25 MHz, or 2.5 MHz transmit clock with
±
50 ppm tolerance based on the selected speed.
Transmit control signals. TX_EN is encoded on the rising
edge of GTX_CLK, TX_ER, XORed with TX_EN is encoded
on this falling edge of GTX_CLK.
Transmit data. In 1000 base-T and 1000 base-X modes,
TXD[3:0] are presented on both edges of GTX_CLK. In
100 base-T and 10 base-T modes, TXD[3:0] are
presented on the rising edge of GTX_CLK.
125 MHz, 25 MHz, or 2.5 MHz receive clock
tolerance derived from the received data stream and
based on the selected speed.
Cyclone III
Device Pin Number
W7
Y6
AB4
W4
AA5
Y5
W3
AA7
Description
±
50
Altera Corporation
March 2008
ppm