Dual Sram Devices - Altera Nios II Cyclone Edition Reference Manual

Dual SRAM Devices

f
Dual SRAM
Devices
1–10
Nios Development Board Reference Manual, Cyclone Edition
Table 1–3. SDRAM (U57) Pin Table (Part 2 of 2)
Pin Name
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM0
DQM1
DQM2
DQM3
RAS_N
CAS_N
CKE
CS_N
WE_N
CLK
See www.micron.com for detailed SDRAM information.
U35 and U36 are two 512 Kbyte x 16-bit asynchronous SRAM devices.
They are connected to the Cyclone device so they can be used by a Nios II
embedded processor as general-purpose memory. The two 16-bit devices
can be used in parallel to implement a 32-bit wide memory subsystem.
Pin Number Connects to Cyclone Pin
31 P4
33 R1
34 R2
36 R6
37 R5
39 R3
40 R4
42 T4
45 T2
47 T3
48 U1
50 U4
51 U2
53 U3
54 V3
56 V2
16 J2
71 J1
28 H4
59 H3
19 H2
18 G3
67 G7
20 G6
17 G4
68 L13
Altera Corporation
December 2004