Altera Cyclone III Reference Manual page 71

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Table 2–51. DDR2 Interface I/O (Part 1 of 6)
Board
Reference
U25, U26 pin K8 Differential clock 0n
U11, U12 pin K8 Differential clock 1n
U13 pin F8 Differential clock 2n
U25, U26 pin J8 Differential clock 0p
U11, U12 pin J8 Differential clock 1p
U13 pin E8 Differential clock 2p
U26 pin F3 Data mask 0
U26 pin B3 Data mask 1
U25 pin F3 Data mask 2
Altera Corporation
March 2008
There are three clock pairs driven from the FPGA to the memories. The
first two pairs clock two memory devices each. The last clock drives the
5th memory device as well as an additional capacitive load to make all
clocks have similar loading.
The maximum frequency is 167 MHz (333 Mb/s per pin). The theoretical
bandwidth of the entire DDR2 interface is 2667 MB/s plus ECC, or 3,000
MB/s raw throughput.
For more information, contact Micron at www.micron.com.
The data interface to the FPGA fabric will run at either one-half or
one-quarter the physical layer data rate when using the Altera DDR2
MegaCore function, which equates to a doubling or quadrupling of the
physical data bus width (144 bits or 288 bits respectively). For example, a
72-bit interface with a 200 MHz external clock speed can have a 200 MHz
144-bit internal bus or a 100 MHz 288-bit interface.
To allow for the use of memory device ODT functionality, the ODT signal
is connected. Because a board-level Class I termination is also available,
use of this feature is optional. Termination resistors are approximately
50 ohms to match the trace impedance of the signals on the board. Clocks
are terminated using a single 100 ohm resistor across each P/N pair.
Altera recommends using the 50 ohm OCT on the FPGA for data, and the
10 mA setting for the address and control pins. The DDR2 devices should
use the reduced drive strength setting available as a register option.
Table 2–51 lists the DDR2 interface signal name, description, and I/O
standard. Signal names and directions are relative to the Cyclone III
FPGA.
Description
Reference Manual
I/O Standard
Signal Name
SSTL18 Class 1
DDR2_CK_N0
SSTL18 Class 1
DDR2_CK_N1
SSTL18 Class 1
DDR2_CK_N2
SSTL18 Class 1
DDR2_CK_P0
SSTL18 Class 1
DDR2_CK_P1
SSTL18 Class 1
DDR2_CK_P2
SSTL18 Class 1
DDR2_DM0
SSTL18 Class 1
DDR2_DM1
SSTL18 Class 1
DDR2_DM2
Cyclone III Development Board
Board Components
Cyclone III
Schematic
Device Pin
Number
AF14
G11
H19
AE14
H12
J19
AH19
AC15
AF8
2–61