Altera Cyclone III Reference Manual page 19

Altera Corporation
March 2008
Table 2–5. MAX II Device Pinout (Part 2 of 9)
MAX II Pin
I/O Standard
Number
1.8 V
F11
2.5 V
A10
1.8 V
G13
1.8 V
L15
1.8 V
K14
1.8 V
M16
1.8 V
L11
1.8 V
M15
1.8 V
L12
1.8 V
J16
2.5 V
E3
2.5 V
D3
2.5 V
C2
2.5 V
N3
2.5 V
N1
2.5 V
N2
2.5 V
P2
2.5 V
E4
2.5 V
C3
1.8 V
N9
1.8 V
T8
1.8 V
N10
1.8 V
R11
1.8 V
P10
1.8 V
T12
1.8 V
M11
1.8 V
R12
1.8 V
N11
1.8 V
T13
1.8 V
P11
1.8 V
R13
1.8 V
T9
1.8 V
M12
Reference Manual
Board Components
Signal
Direction Signal Name
Input
dev_sel
Input
factory_confign
Output
flash_active
Output
flash_byten
Output
flash_cen
Output
flash_oen
Input
flash_rdybsyn
Output
flash_resetn
Output
flash_wen
Input
fpga_bypass
Input
fpga_conf_done
Output
fpga_data
Output
fpga_dclk
Input
fpga_jtag_tck
Output
fpga_jtag_tdi
Input
fpga_jtag_tdo
Input
fpga_jtag_tms
Output
fpga_nconfig
Input
fpga_nstatus
Output
fsa[0]
Output
fsa[1]
Output
fsa[10]
Output
fsa[11]
Output
fsa[12]
Output
fsa[13]
Output
fsa[14]
Output
fsa[15]
Output
fsa[16]
Output
fsa[17]
Output
fsa[18]
Output
fsa[19]
Output
fsa[2]
Output
fsa[20]
Cyclone III Development Board
Schematic
2–9