Table 2–1. Cyclone III Development Board (Part 2 of 3)
Board Reference
Configuration Status and Setup Elements
J6
Device select (DEV_SEL)
jumper
J3
Input
D20 through D24
User LEDs
D25
Configuration done LED
D12 through D15
Channel activity LEDs
J5
Header
D1, D3, D4
Ethernet PHY LEDs
D6
Duplex Ethernet PHY
LED
D5
Power LED
D7, D8
Ethernet PHY
transmit/receive activity
LEDs
SW1
MAX II device control DIP
switch
SW3
JTAG control switch
D17
SRAM active
D23
Flash active
U28
Power display
D16
DDR2 LED
D11
DDR2 LED
Clock Circuitry
Y4
125 MHz
Y5
50 MHz
Y1
24 MHz Crystal
Y2
6 MHz Crystal
Y3
24 MHz
Altera Corporation
March 2008
Type
Sets target device for JTAG signals when using an external
USB Blaster
Type B USB connector that allows for connecting a Type A-B
USB cable between a PC and the board.
Board-specific configuration green LEDs.
Green LED that illuminates when the FPGA is successfully
configured.
Green LEDs that indicate the RX and TX activity on the HSMC
Ports A or B.
Speaker header
Green Ethernet PHY LEDs. Illuminate when Ethernet PHY is
using the 10/100/1000 Mbps (D1, D3, D4) connection speeds.
Green Ethernet PHY LED. Illuminates when Ethernet PHY is
both sending and receiving data.
Blue LED indicates when power is applied to the board.
Green LED. Illuminates when transmit/receive data is active
from the Ethernet PHY.
Controls various features specific to the Cyclone III
development board.
JTAG control DIP switch used to remove or include devices in
the active JTAG chain.
SRAM active LED. Illuminates when the SRAM device is
accessed.
Flash active LED. Illuminates when the flash device is
accessed.
Displays power measured by the MAX II CPLD.
Indicates that the DDR2 top devices are active.
Indicates that the DDR2 bottom devices are active.
125-MHz clock oscillator used for the system clock
50-MHz clock oscillator used for data processing
Cypress USB PHY
USB PHY FTDI reference clock
MAX II device clock
Reference Manual
Description
™
or equivalent.
Cyclone III Development Board
Board Components
2–3
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