Altera Cyclone III Reference Manual page 79

Table 2–53. SRAM Interface I/O (Part 3 of 3)
Board
Reference
U24 pin C6 Data bit 18
U24 pin D5 Data bit 19
U24 pin E5 Data bit 20
U24 pin F5 Data bit 21
U24 pin F6 Data bit 22
U24 pin G6 Data bit 23
U24 pin B1 Data bit 24
U24 pin C1 Data bit 25
U24 pin C2 Data bit 26
U24 pin D2 Data bit 27
U24 pin E2 Data bit 28
U24 pin F2 Data bit 29
U24 pin F1 Data bit 30
U24 pin G1 Data bit 31
f
Altera Corporation
March 2008
Description
Figure 2–14 illustrates the latency for both fixed and variable modes of
operation. For asynchronous accesses, each of the two devices has its own
WAIT pin wired to the Cyclone III device.
For Samsung SRAM pin definitions, data sheet, and other related
documentation, refer to the Samsung website at www.samsung.com.
Reference Manual
I/O Schematic Signal
Standard Name
1.8 V
FSD18
1.8 V
FSD19
1.8 V
FSD20
1.8 V
FSD21
1.8 V
FSD22
1.8 V
FSD23
1.8 V
FSD24
1.8 V
FSD25
1.8 V
FSD26
1.8 V
FSD27
1.8 V
FSD28
1.8 V
FSD29
1.8 V
FSD30
1.8 V
FSD31
Cyclone III Development Board
Board Components
Cyclone III
Device Pin
Number
H14
B8
C8
F7
B11
B22
A18
G8
J12
D9
C9
E7
H10
J10
2–69