Configuration, Status, And Setup Elements; Configuration; Fpga Programming Over Usb - Altera Cyclone III Reference Manual

Configuration,

Status, and
Setup Elements
Altera Corporation
March 2008
This section describes the board's configuration, status, and setup
elements, and is divided into the following groups:
■
Configuration

FPGA programming over USB

●
FPGA programming from flash memory
●
Flash programming over USB
●
■
Status
Board-specific LEDs
●
Power display
●
■
Setup
JTAG control DIP switch
●
MAX II device control DIP switch
●
System reset and configuration push buttons
●
POWER SELECT rotary switch
●
PGM CONFIG SELECT rotary switch
●
Speaker header
●
Configuration
This section discusses FPGA, flash memory, and MAX II device
programming methods supported by the Cyclone III development board.
FPGA Programming Over USB
The FPGA can be programmed at any time the board is powered on using
the USB 2.0 interface and the Quartus II Programmer in JTAG mode.
The JTAG chain is mastered by the embedded USB Blaster function found
in the MAX II device. Only a USB cable is needed to program the
Cyclone III FPGA. Any device can be bypassed by using the appropriate
switch on the JTAG control DIP switch.
1
Board reference SW1 position 5 (SW1.5), labeled MAX0, must be
in the closed position (on) for this feature to properly work. If
the SW1 switch is in the closed position, the PFL megafunction
in the MAX II CPLD may try to overwrite the FPGA image just
downloaded over the USB immediately after completion.
For more information on:
■
Advanced JTAG settings, refer to
■
The JTAG control switch, refer to
page 2–22.
Reference Manual
Board Components
Table 2–7.
"JTAG Control DIP Switch" on
Cyclone III Development Board
2–17