Altera Cyclone III Reference Manual page 22

MAX II CPLD
2–12
Cyclone III Development Board
Table 2–5. MAX II Device Pinout (Part 5 of 9)
MAX II Pin
I/O Standard
Number
GNDIO
T16
1.8 V
J13
2.5 V
M4
2.5 V
K4
1.8 V
H16
2.5 V
H1
2.5 V
B9
1.8 V
E16
2.5 V
D9
1.8 V
N16
1.8 V
L16
1.8 V
N14
1.8 V
M13
1.8 V
N15
1.8 V
L14
2.5 V
J5
1.8 V
M8
2.5 V
J4
2.5 V
J3
2.5 V
K1
1.8 V
K13
1.8 V
M14
1.8 V
P14
2.5 V
K2
1.8 V
K15
1.8 V
H12
2.5 V
M1
2.5 V
L4
2.5 V
L5
2.5 V
M2
1.8 V
N13
1.8 V
H13
1.8 V
H15
Reference Manual
Signal
Direction Signal Name
Gnd
—
Input
hsma_bypass
Output
hsma_jtag_tdi
Input
hsma_jtag_tdo
Input
hsmb_bypass
Output
hsmb_jtag_tdi
Input
hsmb_jtag_tdo
Input
jtag_sel
Output
lcd_bs1
Output
lcd_sern
Input
max_csn
Input
max_dip[0]
Input
max_dip[1]
Input
max_dip[2]
Input
max_dip[3]
Output
max_emb
Input
max_en
Output
max_error
Output
max_factory
Output
max_load
Input
max_oen
Input
max_reserve[0]
Input
max_reserve[1]
Output
max_user
Input
max_wen
Input
max2_clk
Input
maxgp_jtag_tck
Output
maxgp_jtag_tdi
Input
maxgp_jtag_tdo
Input
maxgp_jtag_tms
Input
mwatts_mamps
Input
pgm[0]
Input
pgm[1]
Altera Corporation
Schematic
March 2008